IP Library Granted Patent US 9,608,084
Granted Patent B2
US 9,608,084 · App. 14/926,889 · Granted Mar 28, 2017

Emitter contact epitaxial structure and ohmic contact formation for heterojunction bipolar transistor

Inventors: Timothy S. Henderson (Portland, OR); Sheila K. Hurtt (Portland, OR)
Assignee: Qorvo US, Inc.
H01L29/66318H01L21/76879H01L29/0817H01L29/41708H01L29/42304H01L29/452H01L29/66242H01L29/737H01L29/7371
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Quick Facts
Patent No.
US 9,608,084
App. No.
14/926,889
Granted
Mar 28, 2017
Kind
B2
Abstract

Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device includes a diffusion control layer as part of an emitter epitaxial structure. The IC device may utilize a common metallization scheme to simultaneously form an emitter contact and a base contact. Other embodiments may also be described and/or claimed.

Claims (19)

1. A method comprising:

providing a substrate including a gallium arsenide (GaAs) base layer, an indium gallium phosphide (InGaP) emitter layer on the GaAs base layer, an indium gallium arsenide (InGaAs) layer, and a diffusion control layer on the InGaAs layer, wherein providing the diffusion control layer comprises forming alternating layers of a first material and a second material to create a super lattice structure;

selectively removing material to expose at least a portion of the InGaP emitter layer; and

performing a metallization process to simultaneously form a base contact and an emitter contact.

2. The method of claim 1 , wherein performing the metallization process comprises:

forming a first platinum (Pt) layer on the exposed portion of the InGaP emitter layer and on at least a portion of the diffusion control layer;

forming a titanium (Ti) layer on the first Pt layer;

forming a second Pt layer on the Ti layer; and

forming a gold (Au) layer on the second Pt layer.

3. The method of claim 1 , further comprising applying a mask to define at least a base contact region and an emitter contact region prior to performing the metallization process.

4. A method comprising:

forming a gallium arsenide (GaAs) base layer;

forming an indium gallium phosphide (InGaP) emitter layer on the GaAs base layer;

forming an indium gallium arsenide (InGaAs) layer; and

forming a diffusion control layer on the InGaAs layer, the diffusion control layer comprising a super lattice structure including alternating layers of a first material and a second material.

5. The method of claim 4 , wherein forming the diffusion control layer includes forming a layer of at least one of InGaP, GaAs, indium phosphide (InP), indium aluminum arsenide (InAlAs), aluminum gallium arsenide (AlGaAs), or InGaAs.

6. The method of claim 4 , wherein forming the diffusion control layer includes forming an InGaP layer having a thickness approximately equal to the thickness of the InGaP emitter layer.

7. The method of claim 4 , wherein the first material is InGaAs and the second material is one of GaAs, InP, InAlAs, InGaP or AlGaAs.

8. The method of claim 1 wherein the first material is InGaAs and the second material is one of GaAs, InP, InAlAs, InGaP or AlGaAs.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2016
From: HENDERSON, TIMOTHY S.; HURTT, SHEILA K.
To: QORVO US, INC.
Reel/Frame 039110/0607 →
Continuity (2)
Division 14157096 · Jan 16, 2014
Related Publication 20160049493A1 · Feb 18, 2016