Thin-film transistor array substrate having oxide semiconductor with channel region between conductive regions
View Patent ↗Provided is a method of manufacturing TFT substrate, the method including: forming a first conductive layer and a gate electrode; forming a gate insulating layer covering the first conductive layer and the gate electrode; forming a first contact hole exposing the first conductive layer through the gate insulating layer; forming, on the gate insulating layer of a pixel area, an oxide semiconductor pattern comprising a first region which is conductive, a second region which is conductive, and a third region between the first region and the second region; forming a source electrode contacting the first region of the oxide semiconductor pattern, a drain electrode contacting the second region of the oxide semiconductor pattern and a second conductive layer contacting the first conductive layer on a non-pixel area. Each of the first region and the second region overlaps the gate electrode.
1. A thin film transistor (TFT) substrate comprising:
a first conductive layer on a non-pixel area of a substrate;
a gate electrode on a pixel area of the substrate;
an insulating layer covering the first conductive layer and the gate electrode and comprising a first contact hole exposing the first conductive layer;
an oxide semiconductor pattern on the insulating layer of the pixel area, the oxide semiconductor pattern comprising a first region which is conductive, a second region which is conductive, a third region disposed between the first region and the second region;
a source electrode contacting the first region of the oxide semiconductor pattern and a drain electrode contacting the second region of the oxide semiconductor pattern; and
a second conductive layer on the non-pixel area of the substrate and contacting the first conductive layer via the first contact hole,
wherein each of the first region and the second region overlaps the gate electrode,
wherein each of the source electrode and the drain electrode includes an inner sidewall adjacent to the third region and an outer sidewall far away from the third region,
wherein an outer sidewall of the source electrode and a first sidewall of the oxide semiconductor pattern are disposed along substantially a same line, and an outer sidewall of the drain electrode and a second sidewall of the oxide semiconductor pattern are disposed along substantially a same line, and
wherein a distance between the inner sidewall of the source electrode and the inner sidewall of the drain electrode is greater than a width of the gate electrode.
2. The TFT substrate of claim 1 , wherein the third region overlaps the gate electrode, and
each of an edge of the first region and an edge of the second region overlaps the gate electrode, wherein the first and second regions are adjacent to the third region.
3. The TFT substrate of claim 1 , wherein each of an edge of the source electrode adjacent to the gate electrode and an edge of the drain electrode adjacent to the gate electrode does not overlap the gate electrode.
4. The TFT substrate of claim 3 , wherein a distance between the edge of the source electrode and the gate electrode is from 0 μm to 2 μm.
5. The TFT substrate of claim 4 , wherein a distance between the edge of the drain electrode and the gate electrode is from 0 μm to 2 μm.
6. A thin film transistor (TFT) substrate comprising:
a first conductive layer on a non-pixel area of a substrate;
a gate electrode on a pixel area of the substrate;
an insulating layer covering the first conductive layer and the gate electrode and comprising a first contact hole exposing the first conductive layer;
an oxide semiconductor pattern on the insulating layer of the pixel area, the oxide semiconductor pattern comprising a first region which is conductive, a second region which is conductive, a third region disposed between the first region and the second region;
a source electrode contacting the first region of the oxide semiconductor pattern and a drain electrode contacting the second region of the oxide semiconductor pattern; and
a second conductive layer on the non-pixel area of the substrate and contacting the first conductive layer via the first contact hole,
wherein each of the first region and the second region overlaps the gate electrode,
wherein a sidewall of the source electrode is vertically aligned to a first sidewall of the oxide semiconductor pattern, and a sidewall of the drain electrode is vertically aligned to a second sidewall of the oxide semiconductor pattern, and
wherein the oxide semiconductor pattern further comprises a fourth region which is not processed to be conductive and disposed on a region opposite to the third region with respect to the first region, and a fifth region which is not processed to be conductive and disposed on a region opposite to the third region with respect to the second region.
7. The TFT substrate of claim 6 , wherein the fourth region and the fifth region are disposed to overlap the source electrode and the drain electrode in a plan view, respectively.
8. The TFT substrate of claim 7 , wherein an edge of the fourth region and an edge of the fifth region are aligned with an edge of the source electrode and an edge of the drain electrode, respectively.