IP Library Granted Patent US 9,653,303
Granted Patent B2
US 9,653,303 · App. 14/927,767 · Granted May 16, 2017

Method of manufacturing semiconductor device

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Quick Facts
Patent No.
US 9,653,303
App. No.
14/927,767
Granted
May 16, 2017
Kind
B2
Abstract

In one embodiment, a method of manufacturing a semiconductor device includes forming a structure in which first to N-th insulating layers and first to N-th metal layers are alternately provided on a substrate where N is an integer of two or more. The method further includes processing the first insulating layer. The method further includes forming a first film on a side face of the first insulating layer, the first film containing a first reaction product generated by processing the first insulating layer. The method further includes processing the first metal layer under the first insulating layer, and the second insulating layer under the first metal layer by using the first film as a mask.

Claims (28)

1. A method of manufacturing a semiconductor device, comprising:

forming a structure in which first to N-th insulating layers and first to N-th metal layers are alternately provided on a substrate where N is an integer of two or more;

processing the first insulating layer;

forming a first film on a side face of the first insulating layer, the first film containing a first reaction product generated by processing the first insulating layer; and

processing the first metal layer under the first insulating layer, and the second insulating layer under the first metal layer by using the first film as a mask,

wherein

the first reaction product is generated by a chemical reaction of a substance that forms the first insulating layer, and a first gas used when the first insulating layer is processed; and

the first film is formed in a dry etching apparatus by controlling effective power between electrodes of the dry etching apparatus and selecting the first gas to suppress adhesion of the first film to an upper face of the first metal film.

2. The method of claim 1 , further comprising:

forming a K-th film on a side face of a K-th insulating layer, the K-th film containing a K-th reaction product generated by processing the K-th insulating layer where K is an integer from 2 to N−1; and

processing a K-th metal layer under the K-th insulating layer, and a (K+1)-th insulating layer under the K-th metal layer by using the K-th film as a mask,

wherein

the K-th reaction product is generated by a chemical reaction of a substance that forms the K-th insulating layer, and a first gas used when the K-th insulating layer is processed; and

the K-th film is formed in a dry etching apparatus by controlling effective power between electrodes of the dry etching apparatus and selecting the first gas to suppress adhesion of the K-th film to an upper face of the first metal film.

3. The method of claim 1 , wherein the first gas contains carbon.

4. The method of claim 1 , wherein the first gas contains fluorine or hydrogen.

5. The method of claim 1 , wherein the first gas is a CH 2 F 2 gas, a CHF 3 gas, a C 4 F 6 gas or a C 4 F 8 gas where C represents carbon, F represents fluorine and H represents hydrogen.

6. The method of claim 1 , wherein the first metal layer is processed by using a second gas different from the first gas.

7. The method of claim 6 , wherein the second gas contains carbon.

8. The method of claim 6 , wherein the second gas contains fluorine or hydrogen.

9. The method of claim 6 , wherein the second gas is a CF 4 gas where C represents carbon and F represents fluorine.

10. The method of claim 6 , wherein a composition ratio of fluorine in the first gas is smaller than a composition ratio of fluorine in the second gas.

11. The method of claim 2 , wherein the K-th metal layer is processed by using a second gas different from the first gas.

12. The method of claim 2 , further comprising exposing upper faces of the first to N-th metal layers from the first to N-th insulating layers by processing the first to N-th insulating layers, respectively, and forming first to N-th plugs on the upper faces of the first to N-th metal layers, respectively.

13. The method of claim 1 , wherein the first to N-th metal layers face a semiconductor layer through a first insulator, a charge storage layer and a second insulator.

14. The method of claim 1 , wherein the processing of the first insulating layer, the formation of the first film, and the processing of the first metal layer and the second insulating layer are executed in a same dry etching apparatus.

15. The method of claim 1 , wherein the first insulating layer is processed such that the side face of the first insulating layer is tapered.

16. The method of claim 1 , wherein the first insulating layer is etched such that a selection ratio of the first insulating layer to the first metal layer is five or more.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 29, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043052/0218 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 30, 2015
From: OOSHIMA, KAZUHIRO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 036921/0486 →