IP Library Granted Patent US 9,787,272
Granted Patent B2
US 9,787,272 · App. 14/927,885 · Granted Oct 10, 2017

Linearizing and reducing peaking simultaneously in single-to-differential wideband radio frequency variable gain trans-impedance amplifier (TIA) for optical communication

Inventors: Chakravartula Nallani (San Jose, CA); Rahul Shringarpure (San Jose, CA); Georgios Asmanis (Lake Forest, CA); Faouzi Chaahoub (San Jose, CA); Kishan Venkataramu (Santa Clara, CA)
Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
H03G3/3084H01L31/02016H03F3/08H03G5/28H04B10/40H03F2200/294H03F2200/339
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Quick Facts
Patent No.
US 9,787,272
App. No.
14/927,885
Granted
Oct 10, 2017
Kind
B2
Abstract

An amplifier, a circuit, and an optical communication system are provided. The disclosed amplifier may include a first transistor receiving a first portion of an input signal received at the amplifier, a second transistor receiving a second portion of the input signal, an automatic gain control signal that is dynamically adjustable in response to variations in an output of the amplifier, and a varactor that has its capacitance adjusted by changes in the automatic gain control signal and, as a result, adjusts a position of a pole in a transfer function of the amplifier.

Claims (48)

1. An amplifier, comprising:

a first transistor receiving a first portion of an input signal received at the amplifier;

a second transistor receiving a second portion of the input signal;

an automatic gain control signal that is dynamically adjustable in response to variations in an output of the amplifier; and

a varactor that has its capacitance adjusted by changes in the automatic gain control signal and, as a result, adjusts a position of a pole in a transfer function of the amplifier.

2. The amplifier of claim 1 , further comprising:

a third transistor receiving a bias voltage as an input, an emitter of the third transistor being directly connected to a collector of the first transistor; and

a fourth transistor receiving the bias voltage as an input, an emitter of the fourth transistor being directly connected to a collector of the second transistor, wherein the varactor is connected to both a collector of the third transistor and a collector of the fourth transistor.

3. The amplifier of claim 2 , wherein the automatic gain control signal comprises a control voltage from an automatic gain control loop.

4. The amplifier of claim 3 , wherein an increase in the control voltage from the automatic gain control loop causes a capacitance of the varactor to decrease and wherein a decrease in the control voltage from the automatic gain control loop causes the capacitance of the varactor to increase.

5. The amplifier of claim 2 , wherein the varactor comprises a first terminal directly connected to the collector of the third transistor and a second terminal directly connected to the collector of the fourth transistor.

6. The amplifier of claim 5 , wherein the collector of the third transistor and the collector of the fourth transistor are connected to the control voltage from the automatic gain control loop via a first resistor and second resistor, respectively.

7. The amplifier of claim 5 , further comprising:

a fifth transistor having its base directly connected to the collector of the third transistor and the first terminal of the varactor, wherein an emitter of the fifth transistor outputs an amplified version of the second portion of the input signal; and

a sixth transistor having its base directly connected to the collector of the fourth transistor and the second terminal of the varactor, wherein an emitter of the sixth transistor outputs an amplified version of the first portion of the input signal.

8. The amplifier of claim 1 , further comprising:

a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) connected between an emitter of the first transistor and an emitter of the second transistor and having a gate that receives the automatic gain control signal.

9. A circuit, comprising:

a photodiode configured to receive an optical signal and convert the optical signal into an electrical signal; and

a variable gain amplifier configured to receive the electrical signal or a variant thereof and amplify the received electrical signal or the variant thereof, wherein the variable gain amplifier comprises:

a first transistor;

a second transistor;

an automatic gain control loop that generates a control voltage responsive to variations in an output of the variable gain amplifier; and

a varactor that has its capacitance adjusted by changes in the automatic gain control signal and, as a result, adjusts a position of a pole in a transfer function of the variable gain amplifier.

10. The circuit of claim 9 , wherein the variable gain amplifier further comprises:

a third transistor receiving a bias voltage as an input, wherein an emitter of the third transistor is directly connected to a collector of the first transistor; and

a fourth transistor receiving the bias voltage as an input, wherein an emitter of the fourth transistor is directly connected to a collector of the second transistor, wherein the varactor is connected to both a collector of the third transistor and a collector of the fourth transistor.

11. The circuit of claim 10 , wherein an increase in the control voltage from the automatic gain control loop causes a capacitance of the varactor to decrease and wherein a decrease in the control voltage from the automatic gain control loop causes the capacitance of the varactor to increase.

12. The circuit of claim 10 , wherein the varactor comprises a first terminal directly connected to the collector of the third transistor and a second terminal directly connected to the collector of the fourth transistor.

13. The circuit of claim 12 , wherein the collector of the third transistor and the collector of the fourth transistor are connected to the control voltage from the automatic gain control loop via a first resistor and second resistor, respectively.

14. The circuit of claim 13 , wherein the variable gain amplifier further comprises:

a fifth transistor having its base directly connected to the collector of the third transistor and the first terminal of the varactor, wherein an emitter of the fifth transistor outputs an amplified version of the second portion of the input signal; and

a sixth transistor having its base directly connected to the collector of the fourth transistor and the second terminal of the varactor, wherein an emitter of the sixth transistor outputs an amplified version of the first portion of the input signal.

15. The circuit of claim 9 , further comprising a second variable gain amplifier that receives the output from the variable gain amplifier and provides an amplified version thereof, wherein the second variable gain amplifier comprises a second varactor that has its capacitance adjusted by changes in the automatic gain control signal and, as a result, adjusts a position of a pole in a transfer function of the second variable gain amplifier.

16. An optical communication system, comprising:

an analog front end comprising one or more variable gain amplifiers, the one or more variable gain amplifiers comprising:

a first transistor;

a second transistor;

an automatic gain control loop that generates a control voltage responsive to variations in an output of the analog front end; and

a varactor that has its capacitance adjusted by changes in the automatic gain control signal and, as a result, adjusts a position of a pole in a transfer function of the one or more variable gain amplifiers.

17. The optical communication system of claim 16 , wherein the one or more variable gain amplifiers further comprises:

a third transistor receiving a bias voltage as an input, wherein an emitter of the third transistor is directly connected to a collector of the first transistor; and

a fourth transistor receiving the bias voltage as an input, wherein an emitter of the fourth transistor is directly connected to a collector of the second transistor, wherein the varactor is connected to both a collector of the third transistor and a collector of the fourth transistor.

18. The optical communication system of claim 17 , wherein an increase in the control voltage from the automatic gain control loop causes a capacitance of the varactor to decrease and wherein a decrease in the control voltage from the automatic gain control loop causes the capacitance of the varactor to increase.

19. The optical communication system of claim 17 , wherein the varactor comprises a first terminal directly connected to the collector of the third transistor and a second terminal directly connected to the collector of the fourth transistor.

20. The optical communication system of claim 17 , wherein the variable gain amplifier further comprises:

a fifth transistor having its base directly connected to the collector of the third transistor and the first terminal of the varactor, wherein an emitter of the fifth transistor outputs an amplified version of the second portion of the input signal; and

a sixth transistor having its base directly connected to the collector of the fourth transistor and the second terminal of the varactor, wherein an emitter of the sixth transistor outputs an amplified version of the first portion of the input signal.

Assignments (7)
MERGER Recorded Mar 3, 2023
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED; BROADCOM INTERNATIONAL PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 062952/0850 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2020
From: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
To: BROADCOM INTERNATIONAL PTE. LTD.
Reel/Frame 053771/0901 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 3, 2015
From: NALLANI, CHAKRAVARTULA; SHRINGARPURE, RAHUL; ASMANIS, GEORGIOS; CHAAHOUB, FAOUZI; VENKATARAMU, KISHAN
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037041/0702 →
Continuity (1)
Related Publication 20170126191A1 · May 4, 2017