Discontinuities in a semiconductor device to accommodate for manufacturing variations and/or misalignment tolerances
View Patent ↗An integrated circuit is described as having one or more contact regions to provide one or more interconnections between one or more transistors of the integrated circuit and another integrated circuit. The one or more contact regions represent a self-aligned contact (SAC) whose positioning is determined through one or more patterning processes of a semiconductor fabrication process. The one or more contact regions include one or more contact discontinuities to allow the integrated circuit to accommodate for a wide range of the manufacturing variations and/or the misalignment tolerances by preventing the one or more contact regions from physically contacting other regions, such as gate regions to provide an example, of the one or more transistors. As such, the one or more contact discontinuities have a dynamic size, such as a dynamic area to provide an example, which is dependent upon the manufacturing variations and/or the misalignment tolerances.
1. An integrated circuit, comprising:
a semiconductor substrate;
a first transistor, having a first source/drain region, a second source/drain region, and a first gate region, situated on the semiconductor substrate;
a second transistor, having the second source/drain region, a third source/drain region, and a second gate region, situated on the semiconductor substrate;
an air-gap spacer region situated on the semiconductor substrate, contacting the first gate region, and extending beyond the first gate region in a vertical direction; and
a contact region contacting the second source/drain region and overlapping the air-gap spacer region, the contact region being offset from an approximate center of the second source/drain region by a displacement distance and including a discontinuity to prevent the contact region from physically contacting the first gate region.
2. The integrated circuit of claim 1 , wherein the contact region overlaps the air-gap spacer region in a horizontal direction.
3. The integrated circuit of claim 1 , wherein the first gate region or the second gate region each comprises:
a high dielectric constant (high-κ)/metal-gate (HK/MG) region.
4. The integrated circuit of claim 3 , wherein the HK/MG region comprises:
a high-κ dielectric material; and
a conductive material situated on the high-κ dielectric material.
5. The integrated circuit of claim 1 , wherein the first source/drain region, the second source/drain region, and the third source/drain region comprise:
respective raised source/drain regions situated on the semiconductor substrate.
6. The integrated circuit of claim 1 , further comprising:
a dielectric region situated on the second source/drain region between the contact region and the second gate region.
7. The integrated circuit of claim 6 , wherein the dielectric region comprises:
a high dielectric constant (high-κ) material having a dielectric constant greater than a dielectric constant of silicon dioxide (SiO 2 ).
8. An integrated circuit situated on a semiconductor substrate, comprising:
a transistor, having a first source/drain region, a second source/drain region, and a gate region situated on the semiconductor substrate;
an air-gap spacer region situated on the semiconductor substrate, contacting the gate region, and extending beyond the gate region in a vertical direction; and
a contact region, contacting the second source/drain region and overlapping the air-gap spacer region, offset from an approximate center of the second source/drain region by a displacement distance, the contact region including a discontinuity to prevent the contact region from physically contacting the gate region.
9. The integrated circuit of claim 8 ,
wherein the contact region overlaps the air-gap spacer region in a horizontal direction.
10. The integrated circuit of claim 8 , wherein the gate region comprises:
a high dielectric constant (high-κ)/metal-gate (HK/MG) region.
11. The integrated circuit of claim 10 , wherein the HK/MG region comprises:
a high-κ dielectric material; and
a conductive material situated on the high-κ dielectric material.
12. The integrated circuit of claim 8 , wherein the first source/drain region and the second source/drain region comprise:
respective raised source/drain regions situated on the semiconductor substrate.
13. The integrated circuit of claim 8 , further comprising:
a dielectric region situated on the second source/drain region between the contact region and a second gate region of a second transistor.
14. The integrated circuit of claim 13 , wherein the dielectric region comprises:
a high dielectric constant (high-κ) material having a dielectric constant greater than a dielectric constant of silicon dioxide (SiO 2 ).
15. An integrated circuit situated on a semiconductor substrate, comprising:
a transistor, having a first source/drain region, a second source/drain region, and a gate region, situated on the semiconductor substrate;
an air-gap spacer region situated on the semiconductor substrate, extending beyond the gate region in a vertical direction, and contacting the gate region; and
a contact region contacting the second source/drain region and overlapping the air-gap spacer region, the contact region including a discontinuity to prevent the contact region from physically contacting the gate region.
16. The integrated circuit of claim 15 , wherein the gate region comprises:
a high dielectric constant (high-κ) dielectric material; and
a conductive material situated on the high-κ dielectric material.
17. The integrated circuit of claim 15 , further comprising:
a dielectric region situated on the second source/drain region between the contact region and a second gate region of a second transistor.
18. The integrated circuit of claim 17 , wherein the dielectric region comprises:
a high dielectric constant (high-κ) material having a dielectric constant greater than a dielectric constant of silicon dioxide (SiO 2 ).
19. The integrated circuit of claim 17 , wherein the gate region comprises:
a high dielectric constant (high-κ)/metal-gate (HK/MG) region.
20. The integrated circuit of claim 19 , wherein the HK/MG region comprises:
a high-κ dielectric material; and
a conductive material situated on the high-κ dielectric material.