Transmitting signals between modules
A system comprises a first module and a second module, connected by a transmission line comprising first and second wires. The first module includes common mode voltage circuitry, for imposing a common mode voltage onto the first and second wires. The first module includes signal generation circuitry, for generating a signal voltage in response to first data, and for imposing the signal voltage as a differential signal onto the first and second wires during periods when the first module has first data to transmit. The second module includes current generation circuitry, for generating a signal current in response to second data, and for injecting the signal current as a differential current onto the first and second wires during periods when the second module has second data to transmit. The first module includes respective resistances connected to the first and second wires. The first module includes a first detector for obtaining first output data based on voltages across the resistors resulting from the signal current injected by the current generation circuitry of the second module; and the second module includes a second detector for obtaining second output data based on differential signal imposed by the signal generation circuitry of the first module.
1. A system comprising a first module and a second module, connected by a transmission line comprising first and second wires, wherein at first times the first module has first data to transmit and at second times the second module has second data to transmit, and wherein:
the first module includes common mode voltage circuitry, for imposing a common mode voltage onto the first and second wires at said first times when the first module has first data to transmit and at said second times when the second module has second data to transmit;
the first module includes signal generation circuitry, for generating a signal voltage in response to first data, and for imposing the signal voltage as a differential signal onto the first and second wires during periods when the first module has first data to transmit;
the second module includes current generation circuitry, for generating a signal current in response to second data, wherein, in response to each bit of the second data, the second module generates a signal current having a value that depends on the value of a respective bit of the second data, and for injecting the signal current as a differential current onto the first and second wires during periods when the second module has second data to transmit;
the first module includes respective resistances connected to the first and second wires,
the first module includes a first detector for obtaining first output data based on voltages across the resistors resulting from the signal current injected by the current generation circuitry of the second module; and
the second module includes a second detector for obtaining second output data based on differential signal imposed by the signal generation circuitry of the first module.
2. The system as claimed in claim 1 , wherein the respective resistances of the first module comprise discrete resistors.
3. The system as claimed in claim 1 , wherein the respective resistances of the first module comprise resistors co-integrated with active driver circuitry of the signal generation circuitry.
4. The system as claimed in claim 1 , wherein the respective resistances connected to the first and second wires are matched to a characteristic impedance of the transmission line.
5. The system as claimed in claim 1 , wherein the first module is configured to send data to the second module, and the second module is configured to send data to the first module, in each frame of a plurality of successive frames.
6. The system as claimed in claim 5 , wherein the first module is configured to send control bits to the second module in a first predetermined plurality of frames in a superframe, and the second module is configured to send control bits to the first module in a second predetermined plurality of frames in the superframe.
7. The system as claimed in claim 6 , wherein the first and second modules are configured to send the control bits between data sent from the first module to the second module, and data sent from the second module to the first module, such that there is a single pair of reversals of transmission direction in each frame.
8. The system as claimed in claim 5 , wherein the first module is configured to send synchronization bits to the second module in each frame of a plurality of successive frames.
9. The system as claimed in claim 1 , comprising a plurality of second modules.
10. The system as claimed in claim 1 , wherein the first and second modules are configurable to operate with alternative respective interfaces.
11. The system as claimed in claim 1 , wherein the first and second modules are provided in a single product.
12. The system as claimed in claim 1 , wherein the first module is provided in a host device and the second module is provided in an accessory device.
13. The system as claimed in claim 12 , wherein the accessory device is detachable from the host device.
14. A second module, for use in a system further comprising a first module, connected by a transmission line comprising first and second wires, wherein at first times the first module has first data to transmit and at second times the second module has second data to transmit, and wherein:
the first module includes common mode voltage circuitry, for imposing a common mode voltage onto the first and second wires at said first times when the first module has first data to transmit and at said second times when the second module has second data to transmit;
the first module includes signal generation circuitry, for generating a signal voltage in response to first data, and for imposing the signal voltage as a differential signal onto the first and second wires during periods when the first module has the first data to transmit;
the second module includes current generation circuitry, for generating a signal current in response to second data, wherein, in response to each bit of the second data, the second module generates a signal current having a value that depends on the value of a respective bit of the second data, and for injecting the signal current as a differential current onto the first and second wires during periods when the second module has the second data to transmit;
the first module includes respective resistances connected to the first and second wires,
the first module includes a first detector for obtaining first output data based on voltages across the resistors resulting from the signal current injected by the current generation circuitry of the second module; and
the second module includes a second detector for obtaining second output data based on differential signal imposed by the signal generation circuitry of the first module.