Multi-level output circuit having centralized ESD protection
View Patent ↗An apparatus is described. The apparatus includes an electronic circuit includes multiple supply voltage nodes, an output node and an internal node. The electronic circuit also includes first protection circuitry coupled between the internal node and the output node. The electronic circuit also includes a control circuit coupled to the internal node to bias the internal node. The electronic circuit also includes second protection circuitry coupled to the internal node.
1. An apparatus, comprising:
an electronic circuit comprising:
a) multiple supply voltage nodes that are coupled to one another but not through a gate node of any transistor;
b) an output node;
c) an internal node;
d) first protection circuitry coupled between the internal node and the output node;
e) a control circuit coupled to the internal node to bias the internal node;
f) second protection circuitry coupled to the internal node.
2. The apparatus of claim 1 wherein the control circuit is connected to at least one of the multiple supply voltage node to bias the internal node towards one of the multiple supply voltages.
3. The apparatus of claim 1 wherein the control circuit includes at least one circuit device connected from the internal node to at least one of the multiple supply nodes to selectively switch the internal node to the respective one of the multiple supply nodes.
4. The apparatus of claim 1 wherein the second protection circuitry is coupled to ground.
5. The apparatus of claim 1 wherein more than one output node is coupled to the internal node via a respective first protection circuit.
6. The apparatus of claim 1 wherein the first protection circuitry and the second protection circuitry are to protect the electronic circuit from an ESD strike on the output node.
7. The apparatus of claim 3 further comprising one or more transistors between each of the multiple supply voltage nodes and the output node.
8. The apparatus of claim 1 further comprising a filter coupled to the voltage selector and/or to the internal node.
9. The apparatus of claim 5 wherein the filter is a low pass filter.
10. The apparatus of claim 1 wherein the first protection circuitry comprises a diode.
11. The apparatus of claim 1 wherein the second protection circuitry comprises any of:
a diode;
a varistor;
a transient voltage suppressor;
a thyristor;
a clamping device or circuit;
a ceramic ESD device;
an RC triggered MOS transistor.
12. The apparatus of claim 1 wherein the output of the electronic circuit is a supply voltage rail.
13. An apparatus, comprising:
an electronic circuit, comprising:
a) multiple supply voltage nodes;
b) an output node;
c) an internal node;
d) a selector circuit between the internal node and each of the multiple supply voltage nodes, the selector circuit to provide a greater one of the multiple supply voltages on the internal node;
d) first protection circuitry coupled between the internal node and the output node; and,
e) second protection circuitry coupled to the internal node.
14. The apparatus of claim 13 wherein the electronic circuit is any one of:
a DC/DC converter circuit,
a power management circuit;
an envelope tracker circuit.
15. The apparatus of claim 13 wherein the second protection circuitry is coupled to ground.
16. The apparatus of claim 13 wherein more than one output node is coupled to the internal node via a respective first protection circuit.
17. The apparatus of claim 13 wherein the first protection circuitry comprises a diode.
18. The apparatus of claim 13 wherein the wherein the second protection circuitry comprises any of:
a diode;
a varistor;
a transient voltage suppressor;
a thyristor;
a clamping device or circuit;
a ceramic ESD device;
an RC triggered MOS transistor.
19. A computing system, comprising:
a plurality of processing cores;
a memory controller coupled to a system memory;
a communication interface communicatively coupled to the memory controller;
an electronic circuit comprising:
a) multiple supply voltage nodes that are coupled to one another but not through a gate node of any transistor;
b) an output node;
c) an internal node;
d) first protection circuitry coupled between the internal node and the output node;
e) a control circuit to coupled to the internal node to bias the internal node;
f) second protection circuitry coupled to the internal node.
20. The computing system of claim 19 wherein the electronic circuit is part of any of DC/DC converter circuit, power management circuit or envelope tracker circuit within the computing system.
21. The apparatus of claim 18 wherein the first protection circuitry comprises a diode.
22. The apparatus of claim 18 wherein the wherein the second protection circuitry comprises any of:
a diode;
a varistor;
a transient voltage suppressor;
a thyristor;
a clamping device or circuit;
a ceramic ESD device;
an RC triggered MOS transistor.
23. The apparatus of claim 18 wherein the second protection circuitry is coupled to ground.