Software receive side scaling for packet re-dispatching
View Patent ↗A method of re-dispatching packets at a packet forwarding element that includes a hardware dispatch unit and a multi-core processor. The method, at a first core of the multi-core processor, receives a packet of a particular packet flow from the hardware dispatch unit. The packet is dispatched from the hardware dispatch unit to the first core based on hardware implemented hashing algorithm. The first core identifies the plurality of header fields of the packet that uniquely identifies the particular packet flow. The first core performs a software implemented hashing algorithm on the identified plurality of header fields of the packet to calculate a hash value. The first core re-dispatches the packet from the first core to a second core of the multi-core processor based on the calculated hash value.
1. A method of re-dispatching packets received at a packet forwarding element executing on a device comprising a hardware dispatch unit and a multi-core processor comprising a plurality of processing cores, the method comprising:
receiving a packet of a particular packet flow that the hardware dispatch unit dispatches to a first core of the multi-core processor that is a candidate for re-dispatching to ensure that both encapsulated and non-encapsulated packets of a same flow are processed by a same core;
when the packet is not encapsulated with an overlay-network tunnel header, identifying a first set of header fields of the packet and using a software implemented hashing algorithm to compute a first hash value from the first set of header fields;
when the packet is encapsulated with an overlay-network tunnel header, identifying a different, second set of header fields of the packet and using the software implemented hashing algorithm to compute a second hash value from the second set of header fields; and
re-dispatching the packet from the first core to a second core of the multi-core processor when the computed first or second hash value is mapped to the second core.
2. The method of claim 1 , wherein the software implemented hashing algorithm is performed on at least one of the first and second set of header fields of every packet dispatched to the first core by the hardware dispatch unit.
3. The method of claim 1 , wherein the second set of header fields is an inner set of header fields of the packet that are encapsulated by said overlay network tunnel header.
4. The method of claim 1 further comprising processing the packet at the second core after the packet is re-dispatched from the first core to the second core.
5. The method of claim 4 , wherein processing a packet comprises accessing a set of data structures used for processing the packets of the flow, wherein processing the packets of the particular flow at the second core does not require placing a lock on the data structures used for the packets of the particular flow.
6. The method of claim 1 , wherein the packet forwarding element is a gateway at an edge of a network.
7. The method of claim 1 , wherein the first and second cores are different cores.
8. A non-transitory machine readable medium storing a program for re-dispatching packets received at a packet forwarding element executing on a device comprising a hardware dispatch unit and a multi-core processor comprising a plurality of processing cores, the program executable by a core of the multi-core processor, the program comprising sets of instructions for:
receiving a packet of a particular packet flow that the hardware dispatch unit dispatches to a first core of the multi-core processor that is a candidate for re-dispatching to ensure that both encapsulated and non-encapsulated packets of a same flow are processed by a same core;
when the packet is not encapsulated with an overlay-network tunnel header, identifying a first set of header fields of the packet and using a software implemented hashing algorithm to compute a first hash value from the first set of header fields;
when the packet is encapsulated with an overlay-network tunnel header, identifying a different, second set of header fields of the packet and using the software implemented hashing algorithm to compute a second hash value from the second set of header fields; and
re-dispatching the packet from the first core to a second core of the multi-core processor when the computed first or second hash value is mapped to the second core.
9. The non-transitory machine readable medium of claim 8 , wherein the software implemented hashing algorithm is performed on at least one of the first and second set of header fields of every packet dispatched to the first core by the hardware dispatch unit.
10. The non-transitory machine readable medium of claim 8 , wherein the second set of header fields is an inner set of header fields of the packet that are encapsulated by said overlay network tunnel header.
11. The non-transitory machine readable of claim 8 , the program further comprising a set of instructions for processing the packet at the second core after the packet is re-dispatched from the first core to the second core.
12. The non-transitory machine readable of claim 11 , wherein processing a packet comprises accessing a set of data structures used for processing the packets of the flow, wherein processing the packets of the particular flow at the second core does not require placing a lock on the data structures used for the packets of the particular flow.
13. The non-transitory machine readable of claim 8 , wherein the packet forwarding element is a gateway at an edge of a network.
14. The non-transitory machine readable of claim 8 , wherein the first and second cores are different cores.
15. A host computer comprising:
a hardware dispatch unit;
a multi-core processor comprising a plurality of processing cores;
a non-transitory machine readable medium storing a program for re-dispatching packets received at the packet forwarding element executed by the multi-core processor, the program executed by the multi-core processor, the program comprising sets of instructions for:
receiving a packet of a particular packet flow that the hardware dispatch unit dispatches to a first core of the multi-core processor that is a candidate for re-dispatching to ensure that both encapsulated and non-encapsulated packets of a same flow are processed by a same core;
when the packet is not encapsulated with an overlay-network tunnel header, identifying a first set of header fields of the packet and using a software implemented hashing algorithm to compute a first hash value from the first set of header fields;
when the packet is encapsulated with an overlay-network tunnel header, identifying a different, second set of header fields of the packet and using the software implemented hashing algorithm to compute a second hash value from the second set of header fields; and
re-dispatching the packet from the first core to a second core of the multi-core processor when the computed first or second hash value is mapped to the second core.
16. The host computer of claim 15 , wherein the software implemented hashing algorithm is performed on at least one of the first and second set of header fields of every packet dispatched to the first core by the hardware dispatch unit.
17. The host computer of claim 15 , wherein the second set of header fields is an inner set of header fields of the packet that are encapsulated by said overlay network tunnel header.
18. The host computer of claim 15 , the program further comprising a set of instructions for processing the packet at the second core after the packet is re-dispatched from the first core to the second core.
19. The host computer of claim 18 , wherein processing a packet comprises accessing a set of data structures used for processing the packets of the flow, wherein processing the packets of the particular flow at the second core does not require placing a lock on the data structures used for the packets of the particular flow.
20. The host computer of claim 15 , wherein the packet forwarding element is a gateway at an edge of a network.
21. The host computer of claim 15 , wherein the first and second cores are different cores.