IP Library Granted Patent US 9,503,254
Granted Patent B2
US 9,503,254 · App. 14/930,797 · Granted Nov 22, 2016

Phase locked loop with modified loop filter

Inventors: Kamran Rahbar (Kanata, CA); Peter Crosby (Ottawa, CA)
Assignee: Microsemi Semiconductor ULC
H04L7/0331H03L7/00H03L7/093H04J3/0697
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Quick Facts
Patent No.
US 9,503,254
App. No.
14/930,797
Granted
Nov 22, 2016
Kind
B2
Abstract

A loop filter in a modified phase locked loop has a proportional path generating first output signal that is proportional to an input signal and an integral path for generating a second output signal that is an integral of the input signal. An additional functional path generates a third output signal that is a predetermined function of the input signal. The predetermined function is of the form f(s)/g(s), where f and g are polynomial functions. An adder combines the first, second, and third output signals into a common output signal.

Claims (50)

1. A modified phase locked loop including a loop filter comprising:

a proportional path generating first output signal that is proportional to an input signal;

an integral path for generating a second output signal that is an integral of the input signal;

an additional functional path for generating a third output signal that is a predetermined function of the input signal, said predetermined function being of the form f(s)/g(s), where f and g are polynomial functions; and

an adder configured to combine said first, second, and third output signals into a common output signal and wherein the loop filter has a transfer function H(s) of the form:

H

(

s

)

=

X

1

+

X

2

s

+

X

3

s

wherein

X 1 =2ξω n

X 2 =ω n 2

X 3 =1

and where ξ is the damping factor, and ω n is the natural frequency of the phase locked loop.

2. A method of modifying a phase locked loop including a loop filter with a proportional path generating first output signal that is proportional to an input signal of the look filter and an integral path for generating a second output signal that is an integral of the input signal, said method comprising adding an additional functional path to generate a third output signal that is a predetermined function of the input signal, said predetermined function being of the form f(s)/g(s), where f and g are polynomial functions, and combining said first, second, and third output signals into a common output signal of the loop filter, and wherein the loop filter has a transfer function H(s) of the form:

H

(

s

)

=

X

1

+

X

2

s

+

X

3

s

wherein

X 1 =2ξω n

X 2 =ω n 2

X 3 =1

and where ξ is the damping factor, and ω n is the natural frequency of the phase locked loop.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2025
From: MICROCHIP TECHNOLOGY INC.; MICROCHIP TECHNOLOGY IRELAND LIMITED; MICROSEMI CORPORATION; ATMEL CORPORATION; SILICON STORAGE TECHNOLOGY, INC.; MICROSEMI FREQUENCY AND TIME CORP.; MICROSEMI SEMICONDUCTOR ULC; MICROCHIP TECHNOLOGY GERMANY GMBH
To: CRESTONE IP MANAGEMENT, LLC
Reel/Frame 071991/0419 →
Continuity (3)
Division 14591969 · Jan 8, 2015
Provisional Application 61927013 · Jan 14, 2014
Related Publication 20160094334A1 · Mar 31, 2016