Granted Patent B1

US 9,761,273 · App. 14/930,898 · Granted Sep 12, 2017

Abstract

Claims (103)

1. A data storage device comprising:

a storage medium; and

control circuitry configured to:

first encode first data into a first codeword;

second encode second data into a second codeword, wherein a first code rate of the first codeword is less than a second code rate of the second codeword;

interleave the first codeword and the second codeword to generate an interleaved codeword; and

write the interleaved codeword to the storage medium.

2. The data storage device as recited in claim 1 , wherein a size of the first codeword is less than a size of the second codeword.

3. The data storage device as recited in claim 1 , wherein the control circuitry is further configured to:

read the interleaved codeword from the storage medium to generate a read signal;

sample the read signal to generate signal samples;

process the signal samples with a trellis detector to generate a sequence of reliability metrics representing the interleaved codeword;

de-interleave the sequence of reliability metrics into a first set of reliability metrics representing the first codeword and a second set of reliability metrics representing the second codeword;

decode the first set of reliability metrics to generate a third set of reliability metrics representing the first codeword;

decode the second set of reliability metrics to generate a fourth set of reliability metrics representing the second codeword;

interleave the third set of reliability metrics and the fourth set of reliability metrics to generate interleaved reliability metrics representing the interleaved codeword; and

process the interleaved reliability metrics with the trellis detector.

4. The data storage device as recited in claim 3 , wherein the first code rate of the first codeword increases the accuracy of the trellis detector when processing the interleaved reliability metrics.

5. The data storage device as recited in claim 3 , wherein the trellis detector implements a soft-input soft-output Viterbi algorithm.

6. The data storage device as recited in claim 1 , wherein the first encode and the second encode implement a low density parity check (LDPC) code, the first codeword is a first LDPC codeword, and the second codeword is a second LDPC codeword.

7. The data storage device as recited in claim 1 , wherein the control circuitry is further configured to interleave the first codeword and the second codeword by:

executing a non-uniform interleaving of the first codeword to generate a first non-uniform interleaved codeword;

executing a non-uniform interleaving of the second codeword to generate a second non-uniform interleaved codeword; and

executing a uniform interleaving of the first non-uniform interleaved codeword and the second non-uniform interleaved codeword to generate the interleaved codeword.

8. The data storage device as recited in claim 7 , wherein the interleaved codeword comprises a repeating sequence of symbols of one symbol from the first non-uniform interleaved codeword and at least two symbols from the second non-uniform interleaved codeword.

9. A data storage device comprising:

a storage medium; and

control circuitry configured to:

encode first data into a first codeword;

encode second data into a second codeword;

execute a non-uniform interleaving of the first codeword to generate a first non-uniform interleaved codeword;

execute a non-uniform interleaving of the second codeword to generate a second non-uniform interleaved codeword;

execute a uniform interleaving of the first non-uniform interleaved codeword and the second non-uniform interleaved codeword to generate an interleaved codeword; and

write the interleaved codeword to the storage medium.

10. The data storage device as recited in claim 9 , wherein a size of the first codeword is less than a size of the second codeword.

11. The data storage device as recited in claim 10 , wherein the interleaved codeword comprises a repeating sequence of symbols of one symbol from the first non-uniform interleaved codeword and at least two symbols from the second non-uniform interleaved codeword.

12. The data storage device as recited in claim 9 , wherein a size of the first codeword is the same as the second codeword.

13. A method of operating a data storage device, the method comprising:

first encoding first data into a first codeword;

second encoding second data into a second codeword, wherein a first code rate of the first codeword is less than a second code rate of the second codeword;

interleaving the first codeword and the second codeword to generate an interleaved codeword; and

writing the interleaved codeword to a storage medium.

14. The method as recited in claim 13 , wherein a size of the first codeword is less than a size of the second codeword.

15. The method as recited in claim 13 , further comprising:

reading the interleaved codeword from the storage medium to generate a read signal;

sampling the read signal to generate signal samples;

processing the signal samples with a trellis detector to generate a sequence of reliability metrics representing the interleaved codeword;

de-interleaving the sequence of reliability metrics into a first set of reliability metrics representing the first codeword and a second set of reliability metrics representing the second codeword;

decoding the first set of reliability metrics to generate a third set of reliability metrics representing the first codeword;

decoding the second set of reliability metrics to generate a fourth set of reliability metrics representing the second codeword;

interleaving the third set of reliability metrics and the fourth set of reliability metrics to generate interleaved reliability metrics representing the interleaved codeword; and

processing the interleaved reliability metrics with the trellis detector.

16. The method as recited in claim 15 , wherein the first code rate of the first codeword increases the accuracy of the trellis detector when processing the interleaved reliability metrics.

17. The method as recited in claim 15 , wherein the trellis detector implements a soft-input soft-output Viterbi algorithm.

18. The method as recited in claim 13 , wherein the first encoding and the second encoding implement a low density parity check (LDPC) code, the first codeword is a first LDPC codeword, and the second codeword is a second LDPC codeword.

19. The method as recited in claim 13 , further comprising interleaving the first codeword and the second codeword by:

executing a non-uniform interleaving of the first codeword to generate a first non-uniform interleaved codeword;

executing a non-uniform interleaving of the second codeword to generate a second non-uniform interleaved codeword; and

executing a uniform interleaving of the first non-uniform interleaved codeword and the second non-uniform interleaved codeword to generate the interleaved codeword.

20. The method as recited in claim 19 , wherein the interleaved codeword comprises a repeating sequence of symbols of one symbol from the first non-uniform interleaved codeword and at least two symbols from the second non-uniform interleaved codeword.

21. A method of operating data storage device, the method comprising:

encoding first data into a first codeword;

encoding second data into a second codeword;

executing a non-uniform interleaving of the first codeword to generate a first non-uniform interleaved codeword;

executing a non-uniform interleaving of the second codeword to generate a second non-uniform interleaved codeword;

executing a uniform interleaving of the first non-uniform interleaved codeword and the second non-uniform interleaved codeword to generate an interleaved codeword; and

writing the interleaved codeword to a storage medium.

22. The method as recited in claim 21 , wherein a size of the first codeword is less than a size of the second codeword.

23. The method as recited in claim 22 , wherein the interleaved codeword comprises a repeating sequence of symbols of one symbol from the first non-uniform interleaved codeword and at least two symbols from the second non-uniform interleaved codeword.

24. The method as recited in claim 21 , wherein a size of the first codeword is the same as the second codeword.

25. Control circuitry for use in a data storage device comprising a storage medium, the control circuitry configured to:

first encode first data into a first codeword;

second encode second data into a second codeword, wherein a first code rate of the first codeword is less than a second code rate of the second codeword;

interleave the first codeword and the second codeword to generate an interleaved codeword; and

write the interleaved codeword to the storage medium.

26. The control circuitry as recited in claim 25 , wherein a size of the first codeword is less than a size of the second codeword.

27. The control circuitry as recited in claim 25 , wherein the control circuitry is further configured to:

read the interleaved codeword from the storage medium to generate a read signal;

sample the read signal to generate signal samples;

process the signal samples with a trellis detector to generate a sequence of reliability metrics representing the interleaved codeword;

de-interleave the sequence of reliability metrics into a first set of reliability metrics representing the first codeword and a second set of reliability metrics representing the second codeword;

decode the first set of reliability metrics to generate a third set of reliability metrics representing the first codeword;

decode the second set of reliability metrics to generate a fourth set of reliability metrics representing the second codeword;

interleave the third set of reliability metrics and the fourth set of reliability metrics to generate interleaved reliability metrics representing the interleaved codeword; and

process the interleaved reliability metrics with the trellis detector.

28. The control circuitry as recited in claim 27 , wherein the first code rate of the first codeword increases the accuracy of the trellis detector when processing the interleaved reliability metrics.

29. The control circuitry as recited in claim 27 , wherein the trellis detector implements a soft-input soft-output Viterbi algorithm.

30. The control circuitry as recited in claim 25 , wherein the first encode and the second encode implement a low density parity check (LDPC) code, the first codeword is a first LDPC codeword, and the second codeword is a second LDPC codeword.

31. The control circuitry as recited in claim 25 , wherein the control circuitry is further configured to interleave the first codeword and the second codeword by:

executing a non-uniform interleaving of the first codeword to generate a first non-uniform interleaved codeword;

executing a non-uniform interleaving of the second codeword to generate a second non-uniform interleaved codeword; and

executing a uniform interleaving of the first non-uniform interleaved codeword and the second non-uniform interleaved codeword to generate the interleaved codeword.

32. The control circuitry as recited in claim 31 , wherein the interleaved codeword comprises a repeating sequence of symbols of one symbol from the first non-uniform interleaved codeword and at least two symbols from the second non-uniform interleaved codeword.

33. Control circuitry for use in a data storage comprising a storage medium, the control circuitry configured to:

encode first data into a first codeword;

encode second data into a second codeword;

execute a non-uniform interleaving of the first codeword to generate a first non-uniform interleaved codeword;

execute a non-uniform interleaving of the second codeword to generate a second non-uniform interleaved codeword;

execute a uniform interleaving of the first non-uniform interleaved codeword and the second non-uniform interleaved codeword to generate an interleaved codeword; and

write the interleaved codeword to the storage medium.

34. The control circuitry as recited in claim 33 , wherein a size of the first codeword is less than a size of the second codeword.

35. The control circuitry as recited in claim 34 , wherein the interleaved codeword comprises a repeating sequence of symbols of one symbol from the first non-uniform interleaved codeword and at least two symbols from the second non-uniform interleaved codeword.

36. The control circuitry as recited in claim 33 , wherein a size of the first codeword is the same as the second codeword.

Assignments (8)