Space efficient and power spike resistant ESD power clamp with digitally timed latch
View Patent ↗Embodiments include a system, apparatus, and method for ESD power clamps. Aspects include protecting a circuit using an ESD power clamp device. The ESD power clamp device includes a trigger circuit having a resistor-capacitor network and an inverter stage circuit, wherein the trigger circuit is configured to detect an ESD event. Aspects of the invention further include a timing circuit coupled to the trigger circuit and a timing controlled transistor, wherein the timing circuit controls the timing controlled transistor to prevent the capacitor in the RC network from charging when the timing circuit is initiated. Aspects also include a clamp transistor coupled to the trigger circuit, wherein the clamp transistor is controlled by a signal received from the trigger circuit, and a timing controlled transistor coupled to the trigger circuit and the timing circuit, where the timing controlled transistor switches states based on the output of the timing circuit.
1. A system for protecting a circuit using a clamping device comprising:
a trigger circuit comprising a resistor-capacitor (RC) network and an inverter stage circuit, wherein the trigger circuit is configured to detect an electrostatic discharge (ESD) event;
a clamp transistor coupled to the trigger circuit, wherein the clamp transistor is controlled by a signal received from the trigger circuit;
a timing circuit coupled to the trigger circuit and a timing controlled transistor, wherein the timing circuit controls the timing controlled transistor to prevent the capacitor in the RC network from charging when the timing circuit is initiated; and
the timing controlled transistor coupled to the trigger circuit and the timing circuit, wherein the timing controlled transistor switches states based on an output of the timing circuit.
2. The system of claim 1 , wherein the timing circuit comprises an oscillator circuit and a divider circuit, wherein the oscillator circuit provides an input to the divider circuit and the divider circuit is coupled to the timing controlled transistor.
3. The system of claim 1 , wherein the timing circuit is powered on based on the trigger circuit detecting the ESD event.
4. The system of claim 1 , wherein the timing circuit is activated based on the trigger circuit detecting the ESD event.
5. The system of claim 2 , further comprising a reset circuit for resetting the divider circuit, wherein the reset circuit is coupled to the divider circuit.
6. The system of claim 5 , wherein the reset circuit is coupled to the divider circuit and the gate of the clamp transistor.
7. The system of claim 2 , further comprising a supplemental transistor serially connected to the timing controlled transistor, wherein the supplemental transistor is controlled by an output of the trigger circuit.
8. The system of claim 7 , wherein the supplemental transistor is coupled to ground to prevent the supplemental transistor from being activated by a low voltage signal.
9. A power clamp apparatus for protecting a circuit, comprising:
a trigger circuit comprising an RC network and an inverter stage circuit, wherein the trigger circuit is configured to detect an electrostatic discharge (ESD) event;
a clamp transistor coupled to the trigger circuit, wherein the clamp transistor is controlled by a signal received from the trigger circuit;
a timing circuit coupled to the trigger circuit and a timing controlled transistor, wherein the timing circuit controls the timing controlled transistor to prevent the capacitor in the RC network from charging when the timing circuit is initiated; and
the timing controlled transistor further being coupled to the trigger circuit and the timing circuit, wherein the timing controlled transistor switches states based on an output of the timing circuit.
10. The apparatus of claim 9 , wherein the timing circuit comprises an oscillator circuit and a divider circuit, wherein the oscillator circuit provides an input to the divider circuit and the divider circuit being connected to the timing controlled transistor.
11. The apparatus of claim 9 , wherein the timing circuit is powered on based on the trigger circuit detecting the ESD event.
12. The apparatus of claim 9 , wherein the timing circuit is activated based on the trigger circuit detecting the ESD event.
13. The apparatus of claim 10 , further comprising a reset circuit for resetting the divider circuit, wherein the reset circuit is coupled to the divider circuit.
14. The apparatus of claim 10 , wherein the reset circuit is coupled the gate of the clamp transistor.
15. The apparatus of claim 9 , further comprising a supplemental transistor serially connected to the timing controlled transistor, wherein the supplemental transistor is controlled by an output of the trigger circuit.
16. The system of claim 9 , wherein the supplemental transistor is coupled to ground to prevent the supplemental transistor from being activated by low voltage signal.
17. A method for protecting a circuit using a power clamp device, comprising:
detecting an ESD event by a trigger circuit, wherein the trigger circuit includes an RC network and an inverter stage circuit;
providing, by the trigger circuit, a trigger signal to activate a clamp transistor, wherein the clamp transistor provides a path to discharge an ESD signal; and
generating by a timing circuit a timing signal to control a timing controlled transistor, wherein the timing controlled transistor prevents a capacitor in the RC network from charging for a period of time when the ESD event is detected.
18. The method of claim 17 , wherein the timing circuit comprises an oscillator circuit and a divider circuit.
19. The method of claim 18 , further comprising supplying power to an oscillator circuit and a divider circuit of the timing circuit based on the detection of the ESD event.
20. The method of claim 18 , wherein the timing circuit further comprises a reset circuit coupled to the divider circuit.