Memory device and memory system with sensor
According to one embodiment, a memory device includes a first address memory storing a first address; a controller which is based on a first interface which transmits a signal serially and outputs a first command in accordance with the first interface; and a memory which stores data in a nonvolatile manner, is based on the first interface, and stores received write data in an address based on the first address when the memory receives the first command.
1. A memory device comprising:
memory cells;
an error correction circuit; and
a controller,
wherein, in a write operation:
the error correction circuit receives data to be written to the memory cells, and uses the data and a first matrix to generate a parity, and
the controller writes the data and the parity to the memory cells;
wherein, in a read operation:
the controller reads, from the memory cells, data and parity previously written, and supplies the read data and parity to the error correction circuit,
the error correction circuit receives the read data and parity, and uses the read data and parity and a second matrix to generate a syndrome, and
the error correction circuit uses the syndrome to detect an error of the read data and parity, and to correct an error of the read data when the read data and parity include one-bit or two-bit errors,
wherein the second matrix includes a first and a second portion, the first portion being identical to the first matrix, and the second portion being a unit matrix, and
wherein an XOR of any two columns of the second matrix is different from an XOR of any other two columns of the second matrix and any column of the second matrix.
2. The device of claim 1 , wherein:
the first matrix comprises components in eight rows and eight columns, and
the second matrix comprises components in eight rows and sixteen columns.
3. The device of claim 2 , wherein:
the data to be written comprises components in eight rows and one column, and
the error correction circuit multiplies the first matrix and the data to be written to generate the parity, the generated parity comprising eight rows and one column.
4. The device of claim 2 , wherein:
the second matrix comprises the first matrix in first to eighth columns and the unit matrix in ninth to sixteenth columns,
the read data comprises components in eight rows and one column,
the error correction circuit multiplies the second matrix and an input which comprises the read data in first to eighth rows and the read parity in ninth to sixteenth rows to generate the syndrome, and
the syndrome comprises components in eight rows and one column.
5. The device of claim 4 , wherein:
the first matrix comprises only components of one or zero, and
when the input has an error in a k th row (k being a natural number not greater than sixteen), the syndrome is the same as a k th column of the second matrix.
6. The device of claim 5 , wherein:
when the input has errors in a k th row and h th row (h being a natural number different from k and not greater than sixteen), the syndrome is the same as an XOR of the k th column and an h th column of the second matrix.
7. The device of claim 2 , wherein:
the first matrix comprises:
in an n th row and an m th column, a same component as a component in an (n+1) th row and an (m+1) th column; and
in an eighth row and the m th column, a same component as a component in a first row and an (m+1) th column,
wherein each of m and n is a natural number not greater than seven.