System for designing network on chip interconnect arrangements
A system for designing Network-on-Chip interconnect arrangements includes a Network-on-Chip backbone with a plurality of backbone ports and a set of functional clusters of aggregated IPs providing respective sets of System-on-Chip functions. The functional clusters include respective sub-networks attachable to any of the backbone ports and to any other functional cluster in the set of functional clusters independently of the source map of the Network-on-Chip backbone.
1. A modular platform device, comprising:
a main Network-on-Chip backbone with a plurality of backbone ports;
a backbone memory to store a backbone source map that contains information for routing transactions through the main Network-on-Chip backbone;
a first functional cluster including a first sub-network, at least one IP core, and a first memory, the first sub-network attachable to a first backbone port and attachable to the at least one IP core of the first functional cluster, wherein the first memory is arranged to store a first source map that contains information for routing transactions through the first sub-network; and
a second functional cluster including a second sub-network, at least one IP core, and a second memory, the second sub-network attachable to a second backbone port and attachable to the at least one IP core of the second functional cluster, wherein the second memory is arranged to store a second source map that contains information for routing transactions through the second sub-network.
2. The modular platform device of claim 1 , wherein each attachment of the first sub-network and each attachment of the second sub-network is independent of the backbone source map.
3. The modular platform device of claim 1 , wherein the first functional cluster and the second functional cluster each provide a plurality of System-on-Chip functions.
4. The modular platform device of claim 1 , further comprising:
a third functional cluster including a third sub-network and a third memory, the third sub-network attachable to the second sub-network of the second functional cluster, wherein the third memory is arranged to store a third source map that contains information for routing transactions through the third sub-network.
5. The modular platform device of claim 1 , wherein the first independent local source map includes:
an IP core information item indicative of a source managed locally by the first sub-network; and
a source information item indicative of a System-on-Chip source that identifies a System-on-Chip master.
6. The modular platform device of claim 1 , wherein the first functional cluster and the second functional cluster operate asynchronously.
7. The modular platform device of claim 1 , wherein the first memory is a Contents Addressable Memory.
8. The modular platform device of claim 7 , wherein a size of the Contents Addressable Memory determines a number of outstanding transactions in the first sub-network.
9. The modular platform device of claim 1 , wherein the first memory is a simple memory.
10. The modular platform device of claim 1 , wherein the first source map pairs information associated with the main Network-on-Chip backbone to information associated with the at least one IP core of the first functional cluster.
11. A Network-on-Chip interconnect design method, comprising:
providing a Network-on-Chip backbone with a plurality of backbone ports;
loading a backbone memory with a backbone source map that contains information to route transactions through the Network-on-Chip backbone;
providing a first functional cluster, the first functional cluster including a first sub-network, at least one IP core, and a first memory;
providing a second functional cluster, the second functional cluster including a second sub-network, at least one IP core, and a second memory;
attaching the first sub-network to a first backbone port of the plurality of backbone ports;
attaching the first sub-network to the at least one IP core of the first functional cluster;
loading a first source map in the first memory with information to route transactions through the first sub-network;
attaching the second sub-network to a second backbone port of the plurality of backbone ports;
attaching the second sub-network to the at least one IP core of the second functional cluster; and
loading a second source map in the second memory with information to route transactions through the first sub-network.
12. The Network-on-Chip interconnect design method of claim 11 , wherein providing the first functional cluster includes:
providing a plurality of System-on-Chip functions.
13. The Network-on-Chip interconnect design method of claim 11 , comprising:
providing a third functional cluster, the third functional cluster including a third sub-network, at least one IP core, and a third memory;
attaching the third sub-network to the first sub-network;
loading a third source map in the third memory with information to route transactions through the third sub-network.
14. The Network-on-Chip interconnect design method of claim 13 , comprising:
attaching the third sub-network to the at least one IP core of the third functional cluster.
15. The Network-on-Chip interconnect design method of claim 11 , wherein the first memory is a Contents Addressable Memory.
16. A method carried out with a processor-based system, comprising:
executing computer code with the processor-based system that provides a design of a first System-on-Chip having at least two functional clusters communicatively coupled to a Network-on-Chip backbone, each functional cluster having a sub-network, the first System-on-Chip having a global source map to store information to route transactions through the Network-on-Chip backbone, each sub-network of each functional cluster having an independent source map to store information to route transactions; and
executing computer code with the processor-based system that derives a design of a second System-on-Chip from the design of the first System-on-Chip, wherein at least one of the at least two second System-on-Chip independent local source maps corresponds to at least one of the at least two first System-on-Chip independent local source maps, and wherein at least one of the at least two second System-on-Chip independent local source maps is different from at least one of the at least two first System-on-Chip independent local source maps.
17. The method carried out with a processor-based system of claim 16 , wherein the sub-network of a second functional cluster of the at least two functional clusters is communicatively coupled to the Network-on-Chip backbone through the sub-network of a first functional cluster of the at least two functional clusters.
18. The method carried out with a processor-based system of claim 16 , comprising:
storing at least one independent local source map in a Contents Addressable Memory.
19. The method carried out with a processor-based system of claim 18 , wherein a size of the Contents Addressable Memory determines a possible number of outstanding transactions in a respective sub-network.
20. The method carried out with a processor-based system of claim 16 , wherein the at least two functional clusters of the first System-on-Chip provide different System-on-Chip functions from the at least two functional clusters of the second System-on-Chip.