IP Library Patent Application 14940097
Patent Application
App. No. 14/940,097

Compact and low loss Y-junction for submicron silicon waveguide

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
14/940,097
Abstract

A compact, low-loss and wavelength insensitive Y-junction for submicron silicon waveguides. The design was performed using FDTD and particle swarm optimization (PSO). The device was fabricated in a 248 nm CMOS line. Measured average insertion loss is 0.28±0.02 dB across an 8-inch wafer. The device footprint is less than 1.2 μm×2 μm, orders of magnitude smaller than MMI and directional couplers.

Claims (17)

1 - 8 . (canceled)

9 . A 1×2 power splitter for use in submicron silicon waveguides, comprising:

an input port configured to receive an optical signal having an input power;

a pair of output ports configured to provide substantially equal output signals; and

a tapered waveguide coupling said input port to said output ports comprising a plurality of widths.

10 . The 1×2 power splitter for use in submicron silicon waveguides of claim 9 , wherein said 1×2 power splitter has a minimum feature size of 200 nm.

11 . The 1×2 power splitter for use in submicron silicon waveguides of claim 9 , wherein said 1×2 power splitter is configured to be manufactured using a CMOS fabrication process.

12 . The 1×2 power splitter for use in submicron silicon waveguides of claim 11 , wherein said CMOS fabrication process is a process conducted using a 248 nm scanner.

13 . The 1×2 power splitter for use in submicron silicon waveguides of claim 11 , wherein said CMOS fabrication process is a process conducted using a 193 nm scanner.

14 . The 1×2 power splitter for use in submicron silicon waveguides of claim 9 , wherein said plurality of widths are selected to reduce excess loss.

15 . A method for making a 1×2 power splitter for use in submicron silicon waveguides, comprising the steps of:

configuring an input port to receive an optical signal having an input power;

configuring a pair of output ports to provide substantially equal output signals; and

coupling said input port and to said output ports using a tapered waveguide comprising a plurality of widths.

16 . The method of claim 15 , wherein said plurality of widths can be defined by a numerical algorithm.

17 . The method of claim 16 , wherein said numerical algorithm is a particle swarm optimization.

18 . The method of claim 16 , wherein said numerical algorithm is a genetic algorithm.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 6, 2022
From: ELENION TECHNOLOGIES LLC
To: NOKIA SOLUTIONS AND NETWORKS OY
Reel/Frame 058708/0603 →
CHANGE OF NAME Recorded Dec 8, 2016
From: CORIANT ADVANCED TECHNOLOGY, LLC
To: ELENION TECHNOLOGIES, LLC
Reel/Frame 040852/0121 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 4, 2016
From: ZHANG, YI; YANG, SHUYU; BAEHR-JONES, THOMAS WETTELAND
To: CORIANT ADVANCED TECHNOLOGY, LLC
Reel/Frame 039345/0486 →