Display device
View Patent ↗A display device includes: a pixel region in which plural pixels, each including a light emitting element, a capacitor, a drive transistor, and a switch transistor, are arranged in rows and columns; scanning lines; signal lines; and parasitic capacitance which occurs between a source node of the light emitting element of each of the plural pixels and a signal line among the signal lines, wherein when images having different grayscales are displayed in the pixels on adjacent rows which are a 1st-row pixel and a 2nd-row pixel, a difference between a gate-source voltage of the drive transistor of the 1st-row pixel and a gate-source voltage of the drive transistor of the 2nd-row pixel is less than a voltage value of one grayscale, the difference being represented by ΔVdata×Cad/(Cs+Cad+Coled).
1. A display device comprising:
a pixel region in which plural pixels, each including a light emitting element, a capacitor, a drive transistor, and a switch transistor, are arranged in rows and columns;
scanning lines which supply the plural pixels with control signals for controlling an on-state and an off-state of the switch transistor of each of the plural pixels;
signal lines which supply the plural pixels with image signals for causing the light emitting element of each of the plural pixels to emit light having a desired luminance; and
parasitic capacitance which occurs between a source node of the light emitting element of each of the plural pixels and a signal line among the signal lines, wherein
a 0th-row pixel, a 1st-row pixel, and a 2nd-row pixel included in the plural pixels are connected to the signal line and supplied with a first image signal, a second image signal different from the first image signal, and the second image signal, respectively, and
a difference between a gate-source voltage of the drive transistor of the 1st-row pixel and a gate-source voltage of the drive transistor of the 2nd-row pixel is less than a voltage value of one grayscale, the difference being represented by:
Δ V data× Cad /( Cs+Cad+ Coled)
where ΔVdata denotes a difference between the first image signal supplied to the 0th-row pixel and the second image signal supplied to the 1st-row pixel, Cs denotes capacitance of the capacitor, Cad denotes the parasitic capacitance, and Coled denotes capacitance of the light emitting element.
2. The display device according to claim 1 , wherein
the difference between the gate-source voltage of the drive transistor of the 1st-row pixel and the gate-source voltage of the drive transistor of the 2nd-row pixel is less than 5 mV and greater than 0 mV.
3. The display device according to claim 1 , wherein
an anode electrode of the light emitting element of each of the plural pixels and the signal lines do not overlap when the plural pixels are viewed in a plan view.
4. The display device according to claim 1 , wherein
a conductive layer is disposed between the anode electrode of the light emitting element of each of the plural pixels and the signal lines.
5. A method of operating a display device, the display device including a pixel region, scanning lines, and signal lines, the pixel region including plural pixels arranged in rows and columns, the plural pixels each including a light emitting element, a capacitor, a drive transistor, and a switch transistor, the scanning lines being for supplying the plural pixels with control signals for controlling an on-state and an off-state of the switch transistor of each of the plural pixels, the signal lines being for supplying the plural pixels with image signals for causing the light emitting element of each of the plural pixels to emit light having a desired, the method comprising:
supplying a 0th-row pixel included in the plural pixels with a first image signal via a signal line from among the signal lines during a first time period;
supplying a 1st-row pixel included in the plural pixels with a second image signal via the signal line during a second time period, the second image signal being different from the first image signal; and
supplying a 2nd-row pixel included in the plural pixels with the second image signal via the signal line during a third time period,
wherein parasitic capacitance occurs between a source node of the light emitting element of each of the plural pixels and the signal line among the signal lines,
a difference between a gate-source voltage of the drive transistor of the 1st-row pixel and a gate-source voltage of the drive transistor of the 2nd-row pixel is less than a voltage value of one grayscale, the difference being represented by:
Δ V data× Cad /( Cs+Cad+ Coled)
where ΔVdata denotes a difference between the first image signal supplied to the 0th-row pixel and the second image signal supplied to the 1st-row pixel, Cs denotes capacitance of the capacitor, Cad denotes the parasitic capacitance, and Coled denotes capacitance of the light emitting element.
6. The method according to claim 5 , wherein
the difference between the gate-source voltage of the drive transistor of the 1st-row pixel and the gate-source voltage of the drive transistor of the 2nd-row pixel is less than 5 mV and greater than 0 mV.
7. The method according to claim 5 , wherein
an anode electrode of the light emitting element of each of the plural pixels and the signal lines do not overlap when the plural pixels are viewed in a plan view.
8. The method according to claim 5 , wherein
a conductive layer is disposed between the anode electrode of the light emitting element of each of the plural pixels and the signal lines.