Double-source semiconductor device
View Patent ↗A semiconductor device may include a first source layer, a first insulating layer located over the first source layer, and a first stacked structure located over the first insulating layer. The semiconductor device may include first channel layers passing through the first stacked structure and the first insulating layer. The semiconductor device may include a second source layer including a first region interposed between the first source layer and the first insulating layer and second regions interposed between the first channel layers and the first insulating layer, wherein the second regions of the second source layer directly contact each other.
1. A semiconductor device, comprising:
a first source layer;
a first insulating layer located over the first source layer;
a first stacked structure located over the first insulating layer;
first channel layers passing through the first stacked structure and the first insulating layer; and
a second source layer including a first region interposed between the first source layer and the first insulating layer and second regions interposed between the first channel layers and the first insulating layer, wherein the second regions of the second source layer directly contact each other.
2. The semiconductor device of claim 1 , wherein an upper surface of the second source layer includes at least one groove.
3. The semiconductor device of claim 1 , wherein the second source layer includes at least one void.
4. The semiconductor device of claim 1 , wherein the first insulating layer includes at least one void.
5. The semiconductor device of claim 1 , wherein an upper surface of the second source layer includes at least one groove and the first insulating layer includes at least one void located above the at least one groove.
6. The semiconductor device of claim 1 , wherein an upper surface of the second source layer includes at least one groove and the first insulating layer includes at least one void located in the at least one groove.
7. The semiconductor device of claim 1 , further comprising a memory layer interposed between the first channel layers and the first stacked structure.
8. The semiconductor device of claim 1 , wherein the first stacked structure includes second insulating layers and gate electrodes stacked alternately with each other.
9. The semiconductor device of claim 1 , further comprising:
a second stacked structure located over the first stacked structure;
second channel layers passing through the second stacked structure; and
a coupling pattern surrounding lower portions of the second channel layers and coupling the first channel layers and the second channel layers to each other.
10. The semiconductor device of claim 1 , wherein the first source layer is a region doped with impurities in a substrate.
11. The semiconductor device of claim 1 , wherein the first region of the second source layer directly contacts the first source layer, and the second region of the second source layer directly contacts the first channel layers.
12. The semiconductor device of claim 1 , wherein the second source layer includes a silicon layer or a silicide layer.
13. The semiconductor device of claim 1 , wherein the second regions of the second source layer directly contacts the first channel layers and has a substantially uniform height.
14. The semiconductor device of claim 1 , wherein the first region of the second source layer directly contacts the first source layer and has a substantially uniform height.
15. The semiconductor device of claim 1 , wherein the first region of the second source layer directly contacts the second region of the second source layer.
16. A semiconductor device, comprising:
a source layer including at least one groove on an upper surface;
a stacked structure located over the source layer;
first channel layers passing through the stacked structure and the source layer; and
at least one void located between the source layer and the stacked structure.
17. The semiconductor device of claim 16 , wherein the at least one void is located above the at least one groove.
18. The semiconductor device of claim 16 , further comprising:
an insulating layer located between the source layer and the stacked structure and including the at least one void therein.
19. A semiconductor device, comprising:
a first source layer;
a first insulating layer located over the first source layer;
a first stacked structure located over the first insulating layer;
first channel layers passing through the first stacked structure and the first insulating layer;
second source layers interposed between the first channel layers and the first insulating layer; and
at least one void located between the second source layers and included in the first insulating layer.
20. The semiconductor device of claim 19 , wherein the second source layers are electrically coupled to each other.