Graphene based filler material of superior thermal conductivity for chip attachment in microstructure devices
An integrated circuit chip attachment in a microstructure device is accomplished through the use of an adhesive-based material in which graphene flakes are incorporated. This results in superior thermal conductivity. The spatial orientation of the graphene flakes is controlled, for example by adhering polar molecules to the graphene flakes and exposing the flakes to an external force field, so that the graphene flakes have desired orientations under the integrated circuit chip, alongside of the integrated circuit chip and above the integrated circuit chip.
1. A method, comprising:
positioning a microstructure device chip above a surface of a substrate; and
providing therebetween a filler material that is thermally conductive and comprises graphene flakes, wherein providing comprises depositing said filler material in a deformable state and exposing a first portion of said filler material in said deformable state to a first spatially oriented force field so as to allow graphene flakes in said first portion to take on a first averaged spatial orientation corresponding to said first force field; and
curing said filler material so as to permanently set said first averaged spatial orientation.
2. The method of claim 1 , wherein said thermally conductive filler material comprises a glue substance incorporating therein said graphene flakes.
3. The method of claim 1 , wherein providing comprises, prior to positioning said microstructure device chip above said surface, forming said filler material as a layer above a wafer that comprises a plurality of chips including said microstructure device chip.
4. The method of claim 1 , wherein said thermally conductive filler material completely covers said surface.
5. The method of claim 1 , further comprising exposing a second portion of said filler material to a second spatially oriented force field so as to allow graphene flakes in said second portion to take on a second averaged spatial orientation corresponding to said second force field, wherein curing further permanently sets said second averaged spatial orientation.
6. A method, comprising:
positioning a microstructure device chip above a surface of a substrate; and
providing therebetween a filler material that is thermally conductive and comprises graphene flakes, wherein providing comprises:
providing a first layer; and
providing a second layer adjacent the first layer;
wherein the first and second layer each comprise graphene flakes.
7. The method of claim 6 , wherein providing the first layer comprises:
depositing a layer of said filler material in a deformable state;
exposing said filler material in said deformable state to a first spatially oriented force field so as orient the graphene flakes in a first averaged spatial orientation corresponding to said first force field; and
curing the layer.
8. The method of claim 7 , wherein providing the second layer comprises:
depositing a layer of said filler material in a deformable state;
exposing said filler material in said deformable state to a second spatially oriented force field so as orient the graphene flakes in a second averaged spatial orientation corresponding to said second force field; and
curing the layer.
9. The method of claim 8 , wherein the first and second averaged spatial orientations are perpendicular.
10. The method of claim 8 , wherein the first and second averaged spatial orientations are parallel.
11. The method of claim 10 , further comprising exposing a portion of said filler material in said deformable state for either the first layer or second layer to a third spatially oriented force field so as orient the graphene flakes in said portion in a third averaged spatial orientation corresponding to said third force field and different from the first and second averaged spatial orientations.
12. A method, comprising:
depositing a layer with a filler material that is thermally conductive and comprises graphene flakes on a substrate wafer;
mounting a plurality of semiconductor device chips to the substrate wafer with the deposited layer positioned between each semiconductor device chip and the substrate wafer; and
dicing the substrate wafer to produce a plurality of die structures, with each die structure including at least one semiconductor device chip attached to a diced portion of the substrate wafer by said deposited layer of filler material.
13. The method of claim 12 , wherein depositing comprises depositing said layer of filler material in a deformable state and exposing said filler material in said deformable state to a first spatially oriented force field to orient the graphene flakes with a first averaged spatial orientation corresponding to said first force field.
14. The method of claim 12 , wherein depositing comprises:
depositing said layer of filler material in a deformable state;
exposing first portions of said filler material in said deformable state to a first spatially oriented force field to orient the graphene flakes in the first portions with a first averaged spatial orientation corresponding to said first force field; and
exposing second portions of said filler material in said deformable state to a second spatially oriented force field to orient the graphene flakes in the second portions with a second averaged spatial orientation corresponding to said second force field;
wherein the first and second averaged spatial orientations are different.
15. The method of claim 14 , wherein the first averaged spatial orientation is perpendicular to a mounting surface of said semiconductor device chips and said second averaged spatial orientation is parallel to the mounting surface of said semiconductor device chips.
16. The method of claim 15 , wherein mounting the plurality of semiconductor device chips comprises mounting each semiconductor device chip to a corresponding first portion having graphene flakes oriented with the first averaged spatial orientation.
17. The method of claim 12 , wherein depositing comprises:
depositing a first layer of filler material that is thermally conductive and comprises first graphene flakes;
exposing said filler material of the first layer in said deformable state to a first spatially oriented force field to orient the graphene flakes in the first layer with a first averaged spatial orientation corresponding to said first force field;
depositing a second layer of filler material that is thermally conductive and comprises second graphene flakes; and
exposing said filler material of the second layer in said deformable state to a second spatially oriented force field to orient the graphene flakes in the second layer with a second averaged spatial orientation corresponding to said second force field;
wherein the first and second averaged spatial orientations are different.
18. The method of claim 17 , wherein the second averaged spatial orientation is perpendicular to a mounting surface of said semiconductor device chips and said first averaged spatial orientation is parallel to the mounting surface of said semiconductor device chips.
19. A method, comprising:
depositing, onto a wafer that includes a plurality of semiconductor device integrated circuit chips, a layer with a filler material that is thermally conductive and comprises graphene flakes; and
dicing the wafer to produce a plurality of individual integrated circuit chips, with each individual integrated circuit chip including a diced portion of the wafer covered by a diced portion of the deposited layer of filler material.
20. The method of claim 19 , wherein depositing comprises depositing said layer of filler material in a deformable state and exposing said filler material in said deformable state to a first spatially oriented force field to orient the graphene flakes with a first averaged spatial orientation corresponding to said first force field.
21. The method of claim 19 , wherein depositing comprises:
depositing said layer of filler material in a deformable state;
exposing first portions of said filler material in said deformable state to a first spatially oriented force field to orient the graphene flakes in the first portions with a first averaged spatial orientation corresponding to said first force field; and
exposing second portions of said filler material in said deformable state to a second spatially oriented force field to orient the graphene flakes in the second portions with a second averaged spatial orientation corresponding to said second force field;
wherein the first and second averaged spatial orientations are different.
22. The method of claim 21 , wherein the first averaged spatial orientation is perpendicular to a mounting surface of said semiconductor device chips and said second averaged spatial orientation is parallel to the mounting surface of said semiconductor device chips.
23. The method of claim 22 , wherein mounting the plurality of semiconductor device chips comprises mounting each semiconductor device chip to a corresponding first portion having graphene flakes oriented with the first averaged spatial orientation.
24. The method of claim 19 , wherein depositing comprises:
depositing a first layer of filler material that is thermally conductive and comprises first graphene flakes;
exposing said filler material of the first layer in said deformable state to a first spatially oriented force field to orient the graphene flakes in the first layer with a first averaged spatial orientation corresponding to said first force field;
depositing a second layer of filler material that is thermally conductive and comprises second graphene flakes; and
exposing said filler material of the second layer in said deformable state to a second spatially oriented force field to orient the graphene flakes in the second layer with a second averaged spatial orientation corresponding to said second force field;
wherein the first and second averaged spatial orientations are different.
25. The method of claim 24 , wherein the second averaged spatial orientation is perpendicular to a mounting surface of said semiconductor device chips and said first averaged spatial orientation is parallel to the mounting surface of said semiconductor device chips.