IP Library Granted Patent US 9,425,817
Granted Patent B1
US 9,425,817 · App. 14/946,684 · Granted Aug 23, 2016

High order correction for pulse width modulation (PWM) digital/analog converters with reduced computation

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Quick Facts
Patent No.
US 9,425,817
App. No.
14/946,684
Granted
Aug 23, 2016
Kind
B1
Abstract

A delta sigma modulator (DSM) may be improved by configuring it to set the high-order nonlinear function values to zero when the quantization value being output is at its minimum or maximum value. In one embodiment, a DSM may include at least a quantizer having an input responsive to one of two state variables of the DSM and providing a feedback signal and a modulator output signal. The DSM may also include two mutually nonlinear function blocks, each applying a nonlinear function to the feedback from the quantizer, to form two mutually nonlinear feedback signals. At least one of the nonlinear functions applied by the function blocks may comprise a zero when the modulator output signal is a maximum modulator output signal capable of being output by the quantizer or when the modulator output signal is a minimum modulator output signal capable of being output by the quantizer.

Claims (24)

1. A delta sigma modulator of at least second order, operating at an operating clock rate, having an input and producing an output in response to the input, comprising:

at least two state variables;

a quantizer having an input responsive to one of the state variables and providing a feedback signal and a modulator output signal;

a function block configured to apply nonlinear functions to the feedback from the quantizer to form two mutually nonlinear feedback signals; and

an adder block configured to add one of the nonlinear feedback signals to the input of one of the state variables,

wherein the nonlinear functions applied by the function blocks are substantially linear functions when viewed at a clock rate which is a multiple of the operating clock rate, and

wherein at least one of the nonlinear functions applied by the function block comprises approximately zero when the modulator output signal is a maximum modulator output signal capable of being output by the quantizer or when the modulator output signal is a minimum modulator output signal capable of being output by the quantizer.

2. The modulator of claim 1 , wherein the at least one nonlinear function comprising approximately zero when the modulator output signal is a maximum modulator output signal capable of being output by the quantizer or when the modulator output signal is a minimum modulator output signal capable of being output by the quantizer comprises a quadratic polynomial value.

3. The modulator of claim 1 , wherein the at least one nonlinear function comprising approximately zero when the modulator output signal is a maximum modulator output signal capable of being output by the quantizer or when the modulator output signal is a minimum modulator output signal capable of being output by the quantizer comprises a cubic polynomial value.

4. The modulator of claim 1 , wherein the at least one nonlinear function comprises approximately zero value when a pulse corresponding to the minimum modulator output signal has a zero pulse width and a zero value when a pulse corresponding to the maximum output signal has a full pulse width.

5. The modulator of claim 1 , wherein the nonlinear function blocks comprise read only memories (ROMs).

6. The modulator of claim 1 , wherein the nonlinear function blocks comprise blocks for generating powers of the feedback from the quantizer and scalar multipliers for implementing polynomials.

7. A method for correcting distortion in a delta sigma modulator of at least second order, having at least two state variables responsive to feedback from an output quantizer and operating at an operating clock rate, comprising the steps of:

determining a system equivalent to the modulator, the system operating at a higher clock rate, the higher clock rate being a multiple of the operating clock rate, wherein the output of the system is substantially linear at the higher clock rate;

modeling the response to a system operation at the higher clock rate;

modeling a correction to be applied to each integrator feedback path at the higher clock rate to correct the modelled distortion;

computing the correction to be applied within the modulator at the operating clock rate such that the modulator operating at the operating clock rate substantially matches the operation of the system operating at the higher clock rate in response to the same outputs; and

implementing the computed correction by applying at least two mutually nonlinear functions to the feedback from the quantizer, and adding the respective results to at least two state variables, wherein at least one of the at least two nonlinear functions comprises approximately zero when a modulator output signal is a maximum modulator output signal capable of being output by the quantizer or when the modulator output signal is a minimum modulator output signal capable of being output by the quantizer.

8. The method of claim 7 , wherein the at least one nonlinear function comprising approximately zero when the modulator output signal is a maximum modulator output signal capable of being output by the quantizer or when the modulator output signal is a minimum modulator output signal capable of being output by the quantizer comprises a quadratic polynomial value.

9. The method of claim 7 , wherein the at least one nonlinear function comprising approximately zero when the modulator output signal is a maximum modulator output signal capable of being output by the quantizer or when the modulator output signal is a minimum modulator output signal capable of being output by the quantizer comprises a cubic polynomial value.

10. The method of claim 7 , wherein the at least one nonlinear function comprises approximately zero value when a pulse corresponding to the minimum modulator output signal has a zero pulse width and a zero value when a pulse corresponding to the maximum output signal has a full pulse width.

11. The method of claim 7 , wherein the step of computing the correction includes the steps of determining roots of a state transition matrix and computing the mutually nonlinear functions based on the roots.

12. The method of claim 7 , wherein the step of applying mutually nonlinear functions includes the step of computing powers of the feedback from the quantizer and applying scaling to the powers.

13. The method of claim 7 , wherein the step of applying mutually nonlinear functions includes the step of looking up values in look up tables based upon the feedback from the quantizer.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2017
From: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
To: CIRRUS LOGIC, INC.
Reel/Frame 043990/0143 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2016
From: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD
To: CIRRUS LOGIC INC.
Reel/Frame 039719/0885 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2016
From: MELANSON, JOHN
To: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
Reel/Frame 037583/0492 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2015
From: MELANSON, JOHN
To: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
Reel/Frame 037355/0396 →