Graphical development and deployment of parallel floating-point math functionality on a system with heterogeneous hardware components
View Patent ↗System and method for configuring a system of heterogeneous hardware components, including at least one: programmable hardware element (PHE), digital signal processor (DSP) core, and programmable communication element (PCE). A program, e.g., a graphical program (GP), which includes floating point math functionality and which is targeted for distributed deployment on the system is created. Respective portions of the program for deployment to respective ones of the hardware components are automatically determined. Program code implementing communication functionality between the at least one PHE and the at least one DSP core and targeted for deployment to the at least one PCE is automatically generated. At least one hardware configuration program (HCP) is generated from the program and the code, including compiling the respective portions of the program and the program code for deployment to respective hardware components. The HCP is deployable to the system for concurrent execution of the program.
1. A non-transitory computer accessible memory medium that stores program instructions for configuring a system of heterogeneous hardware components, wherein the program instructions are executable by a processor to:
create a graphical program that includes floating point math functionality, wherein the graphical program comprises a plurality of interconnected nodes that visually indicate functionality of the graphical program, wherein the graphical program is targeted for distributed deployment on a system comprising heterogeneous hardware components, including at least one programmable hardware element and at least one processor;
automatically determine respective portions of the graphical program for deployment to respective ones of the heterogeneous hardware components, including automatically determining respective execution timing for the respective portions;
automatically generate first program code implementing communication functionality between the at least one programmable hardware element and the at least one processor, wherein the first program code is targeted for deployment to the at least one programmable communication element; and
automatically generate at least one hardware configuration program from the graphical program and the first program code, wherein said automatically generating comprises compiling the respective portions of the graphical program and the first program code for deployment to respective ones of the heterogeneous hardware components;
wherein the hardware configuration program is deployable to the system, wherein after deployment, the system is configured to execute portions of the graphical program concurrently, including the floating point math functionality.
2. The non-transitory computer accessible memory medium of claim 1 , wherein the system comprises a heterogeneous system on a chip.
3. The non-transitory computer accessible memory medium of claim 1 , wherein the system comprises a heterogeneous system implemented on multiple chips.
4. The non-transitory computer accessible memory medium of claim 1 , wherein the program instructions are further executable to:
automatically deploy the hardware configuration program to the system.
5. The non-transitory computer accessible memory medium of claim 1 , wherein the at least one processor comprises a digital signal processor (DSP).
6. The non-transitory computer accessible memory medium of claim 1 , wherein the at least one processor comprises at least one graphics processing unit (GPU).
7. The non-transitory computer accessible memory medium of claim 1 , wherein the at least one processor comprises one or more processor for internal communications between the at least one programmable hardware element and the at least one processor.
8. The non-transitory computer accessible memory medium of claim 1 , wherein the at least one processor comprises at least one I/O block for communications between the at least one programmable hardware element and external components or systems.
9. The non-transitory computer accessible memory medium of claim 1 , wherein the system comprises one or more chips, and wherein the at least one processor is configurable for intra-chip communications or inter-chip communications.
10. The non-transitory computer accessible memory medium of claim 1 , wherein the graphical program comprises a graphical data flow program.
11. The non-transitory computer accessible memory medium of claim 1 , wherein the graphical program comprises a plurality of graphical data transfer and synchronization mechanisms represented by graphical floating-point programming nodes, functions, and wires, wherein the graphical data transfer and synchronization mechanisms are deployable to the heterogeneous hardware components, thereby enabling the heterogeneous hardware components implementing the floating-point math functionality to simulate physical systems in which measurements, state-values, inputs, outputs and parameters are shared between the heterogeneous hardware components.
12. The non-transitory computer accessible memory medium of claim 1 , wherein the graphical program comprises multiple models of computation.
13. A method for configuring a system of heterogeneous hardware components, the method comprising:
creating a graphical program that includes floating point math functionality, wherein the graphical program comprises a plurality of interconnected nodes that visually indicate functionality of the graphical program, wherein the graphical program is targeted for distributed deployment on a system comprising heterogeneous hardware components, including at least one programmable hardware element and at least one processor;
automatically determining respective portions of the graphical program for deployment to respective ones of the heterogeneous hardware components, including automatically determining respective execution timing for the respective portions;
automatically generating first program code implementing communication functionality between the at least one programmable hardware element and the at least one processor; and
automatically generating at least one hardware configuration program from the graphical program and the first program code, wherein said automatically generating comprises compiling the respective portions of the graphical program and the first program code for deployment to respective ones of the heterogeneous hardware components;
wherein the hardware configuration program is deployable to the system, wherein after deployment, the system is configured to execute the graphical program concurrently, including the floating point math functionality.
14. The method of claim 13 , wherein the system comprises a heterogeneous system on a chip.
15. The method of claim 13 , wherein the system comprises a heterogeneous system implemented on multiple chips.
16. The method of claim 13 , wherein the at least one processor comprises a digital signal processor (DSP).
17. The method of claim 13 , wherein the at least one processor comprises at least one graphics processing unit (GPU).
18. The method of claim 13 , wherein the graphical program comprises a graphical data flow program.