Semiconductor device including a superlattice and replacement metal gate structure and related methods
View Patent ↗A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.
1. A method for making a semiconductor device comprising:
forming a plurality of spaced apart shallow trench isolation (STI) regions in a substrate;
forming a dummy gate on the substrate between a pair of the STI regions;
forming source and drain regions in the substrate on opposing sides of the dummy gate and between the pair of STI regions;
forming a dielectric layer on the substrate surrounding the dummy gate;
removing the dummy gate and portions of the substrate beneath the dummy gate to define a channel recess in the substrate extending fully between the source and drain regions;
forming a superlattice channel in the channel recess and contacting the source and drain regions, the superlattice channel including a plurality of stacked groups of layers, each group of layers of the superlattice channel comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
forming a replacement gate over the superlattice channel and removing the dielectric layer.
2. The method of claim 1 further comprising performing a well implant in the substrate between the pair of STI regions.
3. The method of claim 1 wherein forming the replacement gate comprises forming a high K dielectric layer over the superlattice channel, and forming a metal gate electrode over the high K dielectric layer.
4. The method of claim 1 wherein each base semiconductor portion comprises silicon.
5. The method of claim 1 wherein each base semiconductor portion comprises germanium.
6. The method of claim 1 wherein the at least one non-semiconductor layer comprises oxygen.
7. The method of claim 1 wherein the at least one non-semiconductor monolayer comprises a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-oxygen.
8. The method of claim 1 wherein the superlattice channel further comprises a base semiconductor cap layer on an uppermost group of layers.
9. The method of claim 1 wherein at least some semiconductor atoms from opposing base semiconductor portions are chemically bound together through the at least one non-semiconductor monolayer therebetween.