Semiconductor memory apparatus and operation method using the same
View Patent ↗A semiconductor memory apparatus includes a command processing block configured to generate a voltage generation start signal, a first write control signal, a second write control signal, a read signal, and an operation signal in response to a first control signal and a second control signal in a write operation, and a memory control block configured to electrically couple a memory block, which stores data, to a sense amplifier or apply a predetermined voltage to the memory block in response to the voltage generation start signal, the first write control signal, the second write control signal, the read signal, and the operation signal.
1. A semiconductor memory apparatus comprising:
a memory cell array configured to include a plurality of memory cells, and store data according to a voltage level of a memory voltage at a memory cell of a position designated by a word line and a bit line;
a voltage supply unit configured to generate the memory voltage when an external command is a write command, and apply the memory voltage to the memory cell array in response to a control signal; and
a data comparison block configured to compare data input from exterior with storage data, and generate the control signal.
2. The semiconductor memory apparatus according to claim 1 , further comprising:
an address input buffer configured to convert an external address input from exterior to an internal address,
an address processing block configured to receive the internal address and generate a row address and a column address,
a row decoding block configured to decode the row address and enable the word line,
a column decoding block configured to decode the column address and enable the bit line, and
a sense amplifier configured to determine a data value of the memory cell designated by the word line and the bit line, and generate the storage data when the external command is the write command.
3. The semiconductor memory apparatus according to claim 2 , wherein, when the external command is the write command, the voltage supply unit generates the memory voltage and simultaneously the sense amplifier compares the input data with the storage data.
4. The semiconductor memory apparatus according to claim 3 , wherein the data comparison block disables the control signal when the input data is substantially equal to the storage data, and enables the control signal when the input data is different from the storage data, and
the voltage supply unit applies the memory voltage to the memory block when the control signal is enabled, and does not apply the memory voltage to the memory block when the control signal is disabled.