Harmonic suppression system

1. A harmonic suppression system, comprising:

an interface connector;

a baseband chip;

an antenna;

an antenna switch;

at least two LC trap networks;

a first differential single-pole multi-throw (SPMT) switch; and

a second differential single-pole multi-throw, SPMT, switch, wherein the interface connector is connected to a common end of the first differential SPMT switch,

wherein a control port of the first differential SPMT switch is connected to a control port of the second differential SPMT switch, the control port of the second differential SPMT switch is connected to the baseband chip, and each gating throw end of multiple gating throw ends of the first differential SPMT switch is connected to each gating throw end of multiple gating throw ends of the second differential SPMT switch in a one-to-one correspondence separately using each LC wave trap network of the at least two LC trap networks,

wherein a common end of the second differential SPMT switch is connected to the baseband chip,

wherein the baseband chip is connected to the antenna using the antenna switch; the baseband chip is configured to determine an operating frequency band of the antenna, and if it is determined that the operating frequency band is one of multiple preset frequency bands, send a preset gating control signal corresponding to the operating frequency band to the control port of the first differential SPMT switch and to the control port of the second differential SPMT switch, wherein each frequency band of the multiple preset frequency bands is in a one-to-one correspondence with each LC trap network of the at least two LC trap networks,

wherein the first differential SPMT switch is configured to electrically connect, according to the preset gating control signal, the interface connector and an LC trap network corresponding to the operating frequency band, and

wherein the second differential SPMT switch is configured to electrically connect, according to the preset gating control signal, the baseband chip and the LC trap network corresponding to the operating frequency band.

2. The system according to claim 1 , wherein the first differential SPMT switch and the second differential SPMT switch further comprise straight-through throw ends, and a straight-through throw end of the first differential SPMT switch is connected to a straight-through throw end of the second differential SPMT switch,

wherein the baseband chip is further configured to send a straight-through control signal to the control port of the first differential SPMT switch and to the control port of the second differential SPMT switch when it is determined that the operating frequency band is not any one of the multiple preset frequency bands,

wherein the first differential SPMT switch electrically connects the interface connector and the straight-through throw end of the first differential SPMT switch according to the straight-through control signal, and

wherein the second differential SPMT switch electrically connects the baseband chip and the straight-through throw end of the second differential SPMT switch according to the straight-through control signal.

3. The system according to claim 2 , wherein the baseband chip is connected to the antenna using a control port of the antenna switch, and wherein the baseband chip is further configured to send, after the operating frequency band of the antenna is determined, a preset antenna switch control signal corresponding to the operating frequency band to the control port of the antenna switch, such that the antenna switch switches a frequency band of an operating signal of the antenna to the operating frequency band according to the preset antenna switch control signal.

4. The system according to claim 2 , wherein each LC trap network comprises:

an LC trap circuit;

a first port connected to the gating throw end of the first differential SPMT switch; and

a second port connected to the gating throw end of the second differential SPMT switch, wherein the first port comprises a first positive port and a first negative port, and the second port comprises a second positive port and a second negative port, wherein the LC trap circuit comprises a first LC trap subcircuit connected between the first positive port and the second positive port and a second LC trap subcircuit connected between the first negative port and the second negative port, wherein the first LC trap subcircuit comprises a first LC parallel circuit and a first capacitor, wherein one end of the first capacitor is connected to a low electrical level, wherein the other end of the first capacitor is connected to the first positive port and to one end of the first LC parallel circuit, wherein the other end of the first LC parallel circuit is connected to the second positive port, wherein the second LC trap subcircuit comprises a second LC parallel circuit and a second capacitor, wherein one end of the second capacitor is connected to a low electrical level, wherein the other end of the second capacitor is connected to the first negative port and to one end of the second LC parallel circuit, wherein the other end of the second LC parallel circuit is connected to the second negative port, wherein an inductor in the first LC parallel circuit and an inductor in the second LC parallel circuit are the same in parameter, wherein a capacitor in the first LC parallel circuit and a capacitor in the second LC parallel circuit are the same in parameter, and wherein the first capacitor and the second capacitor are the same in parameter.

5. The system according to claim 3 , wherein each LC trap network comprises:

an LC trap circuit;

a first port connected to the gating throw end of the first differential SPMT switch; and

a second port connected to the gating throw end of the second differential SPMT switch, wherein the first port comprises a first positive port and a first negative port, and the second port comprises a second positive port and a second negative port, wherein the LC trap circuit comprises a first LC trap subcircuit connected between the first positive port and the second positive port and a second LC trap subcircuit connected between the first negative port and the second negative port, wherein the first LC trap subcircuit comprises a first LC parallel circuit and a first capacitor, wherein one end of the first capacitor is connected to a low electrical level, wherein the other end of the first capacitor is connected to the first positive port and to one end of the first LC parallel circuit, wherein the other end of the first LC parallel circuit is connected to the second positive port, wherein the second LC trap subcircuit comprises a second LC parallel circuit and a second capacitor, wherein one end of the second capacitor is connected to a low electrical level, wherein the other end of the second capacitor is connected to the first negative port and to one end of the second LC parallel circuit, wherein the other end of the second LC parallel circuit is connected to the second negative port, wherein an inductor in the first LC parallel circuit and an inductor in the second LC parallel circuit are the same in parameter, wherein a capacitor in the first LC parallel circuit and a capacitor in the second LC parallel circuit are the same in parameter, and wherein the first capacitor and the second capacitor are the same in parameter.

6. The system according to claim 1 , wherein the baseband chip is connected to the antenna using a control port of the antenna switch, and wherein the baseband chip is further configured to send, after the operating frequency band of the antenna is determined, a preset antenna switch control signal corresponding to the operating frequency band to the control port of the antenna switch, such that the antenna switch switches a frequency band of an operating signal of the antenna to the operating frequency band according to the preset antenna switch control signal.

7. The system according to claim 6 , wherein each LC trap network comprises:

an LC trap circuit;

a first port connected to the gating throw end of the first differential SPMT switch; and

a second port connected to the gating throw end of the second differential SPMT switch, wherein the first port comprises a first positive port and a first negative port, and the second port comprises a second positive port and a second negative port, wherein the LC trap circuit comprises a first LC trap subcircuit connected between the first positive port and the second positive port and a second LC trap subcircuit connected between the first negative port and the second negative port, wherein the first LC trap subcircuit comprises a first LC parallel circuit and a first capacitor, wherein one end of the first capacitor is connected to a low electrical level, wherein the other end of the first capacitor is connected to the first positive port and to one end of the first LC parallel circuit, wherein the other end of the first LC parallel circuit is connected to the second positive port, wherein the second LC trap subcircuit comprises a second LC parallel circuit and a second capacitor, wherein one end of the second capacitor is connected to a low electrical level, wherein the other end of the second capacitor is connected to the first negative port and to one end of the second LC parallel circuit, wherein the other end of the second LC parallel circuit is connected to the second negative port, wherein an inductor in the first LC parallel circuit and an inductor in the second LC parallel circuit are the same in parameter, wherein a capacitor in the first LC parallel circuit and a capacitor in the second LC parallel circuit are the same in parameter, and wherein the first capacitor and the second capacitor are the same in parameter.

8. The system according to claim 1 , wherein each LC trap network comprises:

an LC trap circuit;

a first port connected to the gating throw end of the first differential SPMT switch; and

a second port connected to the gating throw end of the second differential SPMT switch, wherein the first port comprises a first positive port and a first negative port, and the second port comprises a second positive port and a second negative port, wherein the LC trap circuit comprises a first LC trap subcircuit connected between the first positive port and the second positive port and a second LC trap subcircuit connected between the first negative port and the second negative port, wherein the first LC trap subcircuit comprises a first LC parallel circuit and a first capacitor, wherein one end of the first capacitor is connected to a low electrical level, wherein the other end of the first capacitor is connected to the first positive port and to one end of the first LC parallel circuit, and wherein the other end of the first LC parallel circuit is connected to the second positive port, wherein the second LC trap subcircuit comprises a second LC parallel circuit and a second capacitor, wherein one end of the second capacitor is connected to a low electrical level, wherein the other end of the second capacitor is connected to the first negative port and to one end of the second LC parallel circuit, wherein the other end of the second LC parallel circuit is connected to the second negative port, wherein an inductor in the first LC parallel circuit and an inductor in the second LC parallel circuit are the same in parameter, wherein a capacitor in the first LC parallel circuit and a capacitor in the second LC parallel circuit are the same in parameter, and wherein the first capacitor and the second capacitor are the same in parameter.

9. The system according to claim 1 , wherein the interface connector is a Universal Serial Bus (USB) connector.