Multiple range RF amplifier

1. An RF amplifier, comprising:

at least two amplification stages coupled in parallel, each amplification stage comprising at least a first amplifying MOS transistor having a gate connected to a first input node common to all of said amplification stages, having a first source or drain region connected to a first output node common to all of said amplification stages, and having a bulk region insulated from bulk regions of amplifying MOS transistors in other amplification stages; and

a configuration circuit configured to apply to each amplification stage, on a node for biasing the bulk region of said at least the first amplifying MOS transistor of the amplification stage, a voltage for configuring an operating range of the amplification stage, wherein different configuration voltages are applied to different amplification stages,

wherein said at least the first amplifying MOS transistor of each of said at least two amplification stages has a same conductivity type.

2. The amplifier of claim 1 , wherein each amplification stage further comprises a second amplifying MOS transistor having a gate connected to a second input node common to all amplification stages, having a first source or drain region connected to a second output node common to all amplification stages, and having a bulk region connected to the bulk region of the first amplifying MOS transistor of the amplification stage, the first and second amplifying MOS transistors having said same conductivity type.

3. The amplifier of claim 2 , wherein, in each amplification stage, the first and second amplifying MOS transistors form a common-source differential pair.

4. The amplifier of claim 1 , wherein each amplifying MOS transistor has a second source or drain region connected to a node of application of a reference potential common to all amplification stages.

5. The amplifier of claim 1 , wherein said configuration circuit is configured to simultaneously configure at least one amplification stage in class A or class AB, and at least another amplification stage in class B or C.

6. The amplifier of claim 1 , wherein said amplifying MOS transistors are transistors formed in SOI, FDSOI, or FINFET technology.

7. The amplifier of claim 1 , wherein said amplification stages are integrated in a same semiconductor chip.

8. The amplifier of claim 1 , wherein amplifying MOS transistors of different amplification stages have different dimensions.

9. An RF amplifier, comprising:

a class A or class AB amplification stage including a first differential pair of MOS transistors having gate terminals coupled to first and second input nodes, respectively, and having bulk terminals coupled together at a first bias node;

a class B or class C amplification stage including a second differential pair of MOS transistors having gate terminals coupled to said first and second input nodes, respectively, and having bulk terminals coupled together at a second bias node;

wherein the first and second bias nodes are independent of each other; and

a biasing circuit configured to apply a class A or class AB operating bias voltage to the first bias node and apply a class B or class C operating bias voltage to the second bias node.

10. The circuit of claim 9 , wherein each of the first and second differential pairs of MOS transistors further have first conduction nodes coupled in common to a reference supply node and second conduction nodes coupled, respectively, to first and second output nodes.

11. The circuit of claim 9 , wherein each of the first and second differential pairs of MOS transistors is implemented as an integrated transistor device formed in one of SOI, FDSOI, or FINFET technology.

12. The circuit of claim 9 , wherein the first differential pair of MOS transistors and the second differential pair of MOS transistors have different dimensions.

13. The circuit of claim 9 , wherein each of the first and second differential pairs of MOS transistors form a common-source differential pair.

14. An amplifier, comprising:

a first amplification stage including a first differential pair of MOS transistors having gate terminals coupled to first and second input nodes, respectively, and having bulk terminals coupled together at a first bias node;

a second amplification stage including a second differential pair of MOS transistors having gate terminals coupled to said first and second input nodes, respectively, and having bulk terminals coupled together at a second bias node;

wherein MOS transistors of the first and second differential pairs of MOS transistors all have a same conductivity type;

wherein the first and second bias nodes are independent of each other; and

a biasing circuit configured to apply a first operating bias voltage to the first bias node to configure the first amplification stage for operation with a first threshold voltage and apply a second operating bias voltage to the second bias node to configured the second amplification stage for operation with a second threshold voltage different from the first threshold voltage.

15. The circuit of claim 14 , wherein each of the first and second differential pairs of MOS transistors further have first conduction nodes coupled in common to a reference supply node and second conduction nodes coupled, respectively, to first and second output nodes.

16. The circuit of claim 14 , wherein each of the first and second differential pairs of MOS transistors is implemented as an integrated transistor device formed in one of SOI, FDSOI, or FINFET technology.

17. The circuit of claim 14 , wherein the first differential pair of MOS transistors and the second differential pair of MOS transistors have different dimensions.

18. The circuit of claim 14 , wherein each of the first and second differential pairs of MOS transistors form a common-source differential pair.

19. The circuit of claim 14 , wherein operation at the first threshold voltage configures the first amplification stage for operation in one of class A or class AB configuration, and wherein operation at the second threshold voltage configures the second amplification stage for operation in one of class B or class C configuration.

20. An RF amplifier, comprising:

at least two amplification stages coupled in parallel, each amplification stage comprising at least a first amplifying MOS transistor having a gate connected to a first input node common to all of said amplification stages, having a first source or drain region connected to a first output node common to all of said amplification stages, and having a bulk region insulated from bulk regions of amplifying MOS transistors in other amplification stages; and

a configuration circuit configured to apply to each amplification stage, on a node for biasing the bulk region of said at least the first amplifying MOS transistor of the amplification stage, a voltage for configuring an operating range of the amplification stage, wherein different configuration voltages are applied to different amplification stages;

wherein amplifying MOS transistors of different amplification stages have different dimensions.

21. The amplifier of claim 20 , wherein each amplification stage further comprises a second amplifying MOS transistor having a gate connected to a second input node common to all amplification stages, having a first source or drain region connected to a second output node common to all amplification stages, and having a bulk region connected to the bulk region of the first amplifying MOS transistor of the amplification stage.

22. The amplifier of claim 21 , wherein, in each amplification stage, the first and second amplifying MOS transistors form a common-source differential pair.

23. The amplifier of claim 20 , wherein each amplifying MOS transistor has a second source or drain region connected to a node of application of a reference potential common to all amplification stages.

24. An RF amplifier, comprising:

at least two amplification stages coupled in parallel, each amplification stage comprising at least a first amplifying MOS transistor having a gate connected to a first input node common to all of said amplification stages, having a first source or drain region connected to a first output node common to all of said amplification stages, and having a bulk region insulated from bulk regions of amplifying MOS transistors in other amplification stages; and

a configuration circuit configured to apply to each amplification stage, on a node for biasing the bulk region of said at least the first amplifying MOS transistor of the amplification stage, a voltage for configuring an operating range of the amplification stage, wherein different configuration voltages are applied to different amplification stages;

wherein said configuration circuit is configured to simultaneously configure at least one amplification stage in class A or class AB, and at least another amplification stage in class B or C.

25. The amplifier of claim 24 , wherein each amplification stage further comprises a second amplifying MOS transistor having a gate connected to a second input node common to all amplification stages, having a first source or drain region connected to a second output node common to all amplification stages, and having a bulk region connected to the bulk region of the first amplifying MOS transistor of the amplification stage.

26. The amplifier of claim 25 , wherein, in each amplification stage, the first and second amplifying MOS transistors form a common-source differential pair.

27. The amplifier of claim 24 , wherein each amplifying MOS transistor has a second source or drain region connected to a node of application of a reference potential common to all amplification stages.

28. An amplifier, comprising:

a first amplification stage including a first differential pair of MOS transistors having gate terminals coupled to first and second input nodes, respectively, and having bulk terminals coupled together at a first bias node;

a second amplification stage including a second differential pair of MOS transistors having gate terminals coupled to said first and second input nodes, respectively, and having bulk terminals coupled together at a second bias node;

wherein the first differential pair of MOS transistors and the second differential pair of MOS transistors have different dimensions;

wherein the first and second bias nodes are independent of each other; and

a biasing circuit configured to apply a first operating bias voltage to the first bias node to configure the first amplification stage for operation with a first threshold voltage and apply a second operating bias voltage to the second bias node to configured the second amplification stage for operation with a second threshold voltage different from the first threshold voltage.

29. The circuit of claim 28 , wherein each of the first and second differential pairs of MOS transistors further have first conduction nodes coupled in common to a reference supply node and second conduction nodes coupled, respectively, to first and second output nodes.

30. The circuit of claim 28 , wherein each of the first and second differential pairs of MOS transistors is implemented as an integrated transistor device formed in one of SOI, FDSOI, or FINFET technology.

31. The circuit of claim 28 , wherein each of the first and second differential pairs of MOS transistors form a common-source differential pair.

32. An amplifier, comprising:

a first amplification stage including a first differential pair of MOS transistors having gate terminals coupled to first and second input nodes, respectively, and having bulk terminals coupled together at a first bias node;

a second amplification stage including a second differential pair of MOS transistors having gate terminals coupled to said first and second input nodes, respectively, and having bulk terminals coupled together at a second bias node;

wherein the first and second bias nodes are independent of each other; and

a biasing circuit configured to apply a first operating bias voltage to the first bias node to configure the first amplification stage for operation with a first threshold voltage and apply a second operating bias voltage to the second bias node to configured the second amplification stage for operation with a second threshold voltage different from the first threshold voltage; and

wherein operation at the first threshold voltage configures the first amplification stage for operation in one of class A or class AB configuration, and wherein operation at the second threshold voltage configures the second amplification stage for operation in one of class B or class C configuration.

33. The circuit of claim 32 , wherein each of the first and second differential pairs of MOS transistors further have first conduction nodes coupled in common to a reference supply node and second conduction nodes coupled, respectively, to first and second output nodes.

34. The circuit of claim 32 , wherein each of the first and second differential pairs of MOS transistors is implemented as an integrated transistor device formed in one of SOI, FDSOI, or FINFET technology.

35. The circuit of claim 32 , wherein each of the first and second differential pairs of MOS transistors form a common-source differential pair.