SWITCHED POWER STAGE WITH INTEGRATED PASSIVE COMPONENTS
A scalable switching regulator architecture may include an integrated inductor. The integrated inductor may include vias or pillars in a multi-layer substrate, with selected vias coupled at one end by a redistribution layer of the multi-layer substrate and, variously, coupled at another end by a metal layer of a silicon integrated circuit chip or by a further redistribution layer of the multi-layer substrate. The vias may be coupled to the silicon integrated circuit chip by micro-balls, with the vias and micro-balls arranged in arrays.
1 . A package including an integrated circuit, comprising:
an integrated circuit (IC) chip including a system-on-chip (SoC) and a voltage regulator, the voltage regulator including first and second transistors connected in series;
a multi-layer substrate coupled to the IC chip by micro-bumps, including at least one array of micro-bumps, the multi-layer substrate including at least one redistribution layer and a plurality of vias, with selected vias extending from selected ones of the micro-bumps of the at least one array of micro-bumps coupled by the at least one redistribution layer in pairs, with the selected vias electrically coupled to others of the selected vias about the micro-bumps;
wherein the selected vias and the micro-bumps of the at least one array of micro-bumps form at least part of an inductor structure; and
wherein the at least part of an inductor structure is positioned to correspond to a layout area of the first and second transistors of the voltage regulator.
2 . The package including an integrated circuit of claim 1 , wherein the multi-layer substrate includes a redistribution layer electrically coupling the selected vias to others of the selected vias about the micro-bumps.
3 . The package including an integrated circuit of claim 1 , wherein a metal layer of the IC chip electrically couples the selected vias to others of the selected vias about the micro-bumps.
4 . The package including an integrated circuit of claim 1 , wherein the at least one array of micro-bumps are arranged in a pattern and connected so as to form at least one closed loop magnetic field during operation of the IC chip.
5 . The package including an integrated circuit of claim 1 , wherein the micro-bumps include micro-bumps for power and ground connections, and the micro-bumps for power and ground connections are about opposite sides of the at least one array of micro-bumps.
6 . The package including an integrated circuit of claim 1 , wherein the at least one array of micro-bumps includes a first array of micro-bumps and a second array of micro-bumps, each of the first array of micro-bumps and the second array of micro bumps including a first set of micro-bumps and a second set of micro-bumps, the first set of micro-bumps being arranged in a pair of parallel lines, the second set of micro-bumps being arranged in a further pair of parallel lines parallel to the pair of parallel lines, the lines of the further parallel lines being separated by the pair of parallel lines of the first set of micro-bumps, the first set of micro-bumps of the first and second micro-bump arrays being configured for passage of current in a first direction and the second set of micro-bumps of the first and second micro-bump arrays being configured for passage of current in a second direction, the second direction opposite the first direction.
7 . The package including an integrated circuit of claim 6 , wherein the at least one array of micro-bumps includes a third array of micro-bumps between the first array of micro-bumps and the second array of micro-bumps, the third array of micro-bumps including the first set of micro-bumps and the second set of micro-bumps, the first set of micro-bumps of the third micro-bump array being configured for passage of current in the second direction and the second set of micro-bumps of the third micro-bump array being configured for passage of current in the first direction.
8 . The package including an integrated circuit of claim 1 , wherein a volume of the multi-layer substrate defined by the selected ones of the vias includes a magnetic material.
9 . The package including an integrated circuit of claim 8 , wherein the magnetic material is a ferrite.
10 . A method for use in providing a system-on-chip (SoC) including an embedded voltage regulator, comprising:
forming a redistribution layer for a multi-layer substrate;
forming at least one array of vias in the multi-layer substrate, the at least one array of vias forming at least part of an inductor, at least some of the vias of the at least one array of vias electrically connected by connections provided by the redistribution layer;
depositing a magnetic material between vias of the at least one array of vias;
connecting an IC chip including the voltage regulator to the at least one array of vias, the IC chip connected to the at least one array of vias by at least one array of micro-bumps, the at least one array of micro-bumps underlying a layout of switching transistors of the voltage regulator, at least some of the micro-bumps electrically connected by connections provided by a metal layer of the IC chip, the at least one array of vias, the at least one array of micro-bumps, the connections provided by the redistribution layer and the connections provided by the metal layer forming an inductor.
11 . The method of claim 10 further comprising forming connections between the multi-layer substrate and a printed circuit board using a plurality of solder balls on the substrate.
12 . The method of claim 10 , wherein the at least one array of vias comprises a first array of vias and a second array of vias, with the connections provided by the metal layer of the IC chip and the connections provided by the redistribution layer arranged such that current flowing in a first set of vias of the first array of vias and the second array of vias would flow in a direction opposite to that of a second set of vias of the first array of vias and the second array of vias, with, for each array, vias of the first set of vias being flanked by vias of the second set of vias.
13 . The method of claim 12 , wherein each of the first and second sets of vias includes vias linearly arranged.
14 . The method of claim 10 , wherein the magnetic material comprises ferrite.
15 . The method of claim 12 , further comprising forming a plurality of third vias providing a power supply path and a plurality of fourth vias providing a ground path, with the plurality of third vias and the plurality of fourth vias on opposing sides of the first array of vias and the second array of vias.
16 . The method of claim 12 , wherein the voltage regulator includes a high side switch and a low side switch coupled in series, between a higher voltage source and a lower voltage source, and the IC chip is connected to the vias such that the high side switch and the low side switch overlay the first array of vias and the second array of vias.
17 . The method of claim 16 , wherein the voltage regulator further includes a bypass switch coupling an inductor node to a load output node.
18 . The method of claim 17 , wherein the connections provided by the redistribution layer and the metal layer of the IC chip serve to provide connections to maximize inductance applied to a signal on the inductor node and minimize inductance applied to signals from the higher voltage source and the lower voltage source.