IP Library Granted Patent US 9,893,193
Granted Patent B2
US 9,893,193 · App. 14/956,780 · Granted Feb 13, 2018

Thin-film transistor including a gate electrode with a side wall insulating layer and display device

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Quick Facts
Patent No.
US 9,893,193
App. No.
14/956,780
Granted
Feb 13, 2018
Kind
B2
Abstract

A method of fabricating a thin-film transistor includes: forming an oxide semiconductor layer above a substrate; forming a gate insulating layer above the oxide semiconductor layer; forming a gate electrode above the gate insulating layer; forming a cover layer on the gate electrode; forming a side wall insulating layer on a side wall portion of the gate electrode by heat treatment, after the forming of a cover layer; forming an interlayer insulating layer covering the gate electrode and the oxide semiconductor layer, after the forming of a side wall insulating layer; and forming, above the interlayer insulating layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer.

Claims (22)

1. A thin-film transistor comprising:

an oxide semiconductor layer having a channel region, a source region, and a drain region, the source region and the drain region each having a resistivity lower than a resistivity of the channel region;

a gate insulating layer disposed above the oxide semiconductor layer;

a gate electrode disposed at a position that is above the gate insulating layer and opposing the channel region, the gate electrode having a conductive region and side wall insulating regions at each side of the conductive region;

a metal oxide layer disposed to contact the side wall insulating regions;

an interlayer insulating layer covering the gate electrode and the oxide semiconductor layer;

a cover layer disposed between the gate electrode and the interlayer insulating layer; and

a source electrode and a drain electrode disposed above the interlayer insulating layer and connected to the source region and the drain region, respectively,

wherein the side wall insulating regions of the gate electrode include, as a main component, an oxide of a metal included in the conductive region of the gate electrode,

electrical conductivity between the gate electrode and the metal oxide layer is inhibited by the side wall insulating regions,

the side wall insulating regions of the gate electrode include thermally oxidized material and

side surfaces of the cover layer, edges of the side wall insulating regions, and edges of the channel region are flush with one another.

2. The thin-film transistor according to claim 1 ,

wherein the metal oxide layer is further disposed on the oxide semiconductor layer and in contact with the source region and the drain region, and

the metal oxide layer includes, as a main component, an oxide of a second metal whose bond dissociation energy with oxygen is greater than a bond dissociation energy with oxygen of a first metal included in the oxide semiconductor layer.

3. The thin-film transistor according to claim 2 , wherein

the first metal is one of indium, gallium, and zinc, and

the second metal is aluminum.

4. A display device comprising the thin-film transistor according to claim 1 .

5. The thin-film transistor according to claim 1 , wherein a surface region of the oxide semiconductor layer in contact with the metal oxide layer is removed of oxygen to reduce its oxygen content when the top surface region is in contact with the metal oxide layer.

6. The thin-film transistor according to claim 1 , wherein a surface region of the metal oxide layer in contact with the oxide semiconductor layer is infused with oxygen to increase its oxygen content when the bottom surface region is in contact with the oxide semiconductor layer.

7. The thin-film transistor according to claim 1 , wherein the metal oxide contacts the source region and the drain region of the oxide semiconductor layer.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 2, 2015
From: KANEGAE, ARINOBU; FUKUI, YUSUKE
To: PANASONIC CORPORATION
Reel/Frame 037191/0708 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 2, 2015
From: KOBAYASHI, EMI
To: JOLED INC.
Reel/Frame 037192/0652 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 2, 2015
From: PANASONIC CORPORATION
To: JOLED INC.
Reel/Frame 037191/0796 →