Heat sink package
This invention minimizes the thermal resistance and maximizes the power density of a power transistor by mounting the transistor in flip-chip fashion on a heat sink/heat spreader and conducting the heat from the active semiconductor layer through the heat sink/heat spreader (as opposed to through the low conductivity substrate). Illustratively, the semiconductor device package comprises: a high electron mobility transistor (HEMT) formed in a layer of Gallium Nitride (GaN) having a first major surface; at least one metal contact pad making thermal contact with the layer of GaN on its first major surface; a heat sink/heat spreader in electrical and thermal contact with the contact pad(s) on the first surface; and a substrate on which the heat sink is mounted.
1. A semiconductor device package comprising:
a silicon substrate for supporting an integrated circuit mounted in a flip-chip fashion;
a high electron mobility transistor (HEMT) formed in a layer of Gallium Nitride (GaN) having a first major active device surface mounted in the flip-chip fashion on the silicon substrate;
an interconnect making thermal contact with the layer of GaN on its first major active device surface, said interconnect comprising a high areal density ohmic contact layer covering a high percentage of the first major active device surface;
a first high areal density heat sink/heat spreader disposed across a majority of the interconnect, and in electrical and thermal contact with said interconnect; and
a second high areal density heat sink/heat spreader embedded within the silicon substrate and in electrical and thermal contact with the first heat sink/heat spreader.
2. The device package of claim 1 where the first heat sink/heat spreader is made of copper.
3. The device package of claim 1 wherein the silicon substrate is a laminate.
4. The device package of claim 1 wherein the silicon substrate provides for surface mounting.
5. A semiconductor device package comprising:
a silicon substrate for supporting a transistor mounted in a flip-chip fashion;
a transistor formed in a layer of III-V semiconductor material having a first major active device surface mounted in the flip-chip fashion on the silicon substrate;
an interconnect making thermal contact with the layer of III-V semiconductor material on its first major active device surface, said interconnect comprising a high areal density ohmic contact layer covering a high percentage of the first major active device surface;
a first high areal density heat sink/heat spreader disposed across a majority of the interconnect and in electrical and thermal contact with said interconnect; and
a second high areal density heat sink/heat spreader embedded within the silicon substrate and in electrical and thermal contact with the first heat sink/heat spread.
6. The device package of claim 5 wherein the first heat sink/heat spreader is made of copper.
7. The device package of claim 5 , wherein the silicon substrate is a laminate.
8. The device package of claim 5 wherein the silicon substrate provides for surface mounting.
9. A chip scale GaN common source GaN high electron mobility transistor (HEMT) amplifier with one or more integrated high areal density conductive heat spreaders formed across a majority of an active semiconductor surface of a semiconductor die to provide thermal uniformity across the semiconductor die, wherein the one or more integrated high areal density conductive heat spreaders is thermally attached using sintered silver to a solid metal heat sink/heat spreader that is embedded inside a carrier substrate.
10. The device of claim 9 wherein the one or more integrated high areal density conductive heat spreaders are formed in batch processes.
11. The device of claim 9 wherein additional passive and/or active components and packages are integrated onto and/or into the carrier substrate to perform an additional function selected from the group consisting of matching, biasing, and bypassing.
12. The device of claim 11 wherein the additional passive and/or active components include SMD capacitors, CMOS logic die, Lange couplers, quarter wave transmission line transformers and/or impedance inverters.
13. The device of claim 9 wherein the GaN HEMT is configured in cascade with a common emitter HBT (Hetero-Junction Bipolar Transistor).