Wideband polar receiver architecture and signal processing methods
Wideband polar receivers and method of operation are described. A phase-modulated input signal is received at a polar receiver that includes an injection-locked oscillator. The injection-locked oscillator includes a plurality of injection points. Based on the frequency of the input signal, a particular Nth harmonic is selected, and the input signal is injected at the set of injection points corresponding to the selected Nth harmonic. The injection-locked oscillator generates an oscillator output signal, and the phase of the input signal is determined from the phase of the oscillator output signal. In some embodiments, the oscillator output signal is frequency-multiplied by N, mixed with the input signal, and filtered for use in amplitude detection. The input signal is decoded based on the phase and amplitude information.
1. A method comprising:
receiving a phase-modulated input signal at a polar receiver including an injection-locked oscillator;
operating the injection-locked oscillator to generate an oscillator output signal while injecting the input signal into the injection-locked oscillator at a set of injection points corresponding to an Nth harmonic of the injection-locked oscillator, where N is an integer;
multiplying a frequency of the oscillator output signal by a factor of N to generate a frequency-multiplied oscillator signal;
mixing the frequency-multiplied oscillator signal with the input signal to generate a mixed signal;
filtering the mixed signal; and
sampling the filtered mixed signal.
2. The method of claim 1 , wherein N is an integer greater than one.
3. The method of claim 1 , further comprising selecting the value N such that the frequency of the phase-modulated signal is substantially an Nth harmonic of a frequency within a locking range of the injection-locked oscillator.
4. The method of claim 1 , further comprising tuning a free-running frequency of the injection-locked oscillator such that the frequency of the phase-modulated signal is substantially an Nth harmonic of the free-running frequency.
5. The method of claim 1 , further comprising measuring a phase of the oscillator output.
6. The method of claim 1 , further comprising:
based on the frequency of the input signal, selecting one of a plurality band-specific amplifiers; and
amplifying the input signal with the selected one of the band-specific amplifiers prior to injecting the input signal.
7. The method of claim 1 , wherein the oscillator includes at least two phase-shifted output taps, and wherein multiplying the frequency of the oscillator output includes combining signals from the phase-shifted output taps with an XOR gate.
8. A method of generating an amplitude-limited replica of an RF input signal, the method comprising:
injecting the RF input signal at an Nth harmonic input of an injection-locked oscillator, where a frequency of the RF input signal is substantially N times a fundamental frequency of the injection-locked oscillator;
while injecting the RF input signal, operating the injection-locked oscillator to generate an oscillator output signal having multiple phases; and
frequency-multiplying the oscillator output signal by a factor of N by combining the multiple phases of the oscillator output signal to generate the amplitude-limited replica signal.
9. The method of claim 8 , wherein the injection-locked oscillator is a ring oscillator including a plurality of sequential buffers.
10. The method of claim 9 , wherein frequency-multiplying the oscillator output signal includes combining a first buffer output of a first one of the buffers and a second buffer output of a second one of the buffers with an XOR operation.
11. The method of claim 8 , further comprising selecting a value of N based on the frequency of the input signal.
12. The method of claim 8 , wherein N is an integer greater than one.
13. An envelope elimination circuit for generating an amplitude-limited replica of an RF input signal, the circuit comprising:
an injection-locked oscillator having an Nth harmonic input and an oscillator output having multiple phases, the Nth harmonic input being adapted to receive the RF input signal;
a frequency multiplier having an input and a frequency-multiplied output, the input being connected to the oscillator output, wherein the frequency multiplier is operative to frequency-multiply the input by a factor of N by combining multiple phases of the oscillator output signal, and wherein the frequency-multiplied output is operative to provide the amplitude-limited replica of the RF input signal.
14. The circuit of claim 13 , wherein the injection-locked oscillator is a ring oscillator including a plurality of sequential buffers.
15. The circuit of claim 14 , wherein the frequency multiplier includes an XOR circuit having a first XOR input connected to a first buffer output of a first one of the buffers and a second XOR input connected to a second buffer output of a second one of the buffers.
16. The circuit of claim 13 , wherein the injection-locked oscillator includes a plurality of sets of injection points, each set of injection points corresponding to a different harmonic of the injection-locked oscillator.
17. The circuit of claim 13 , further comprising a controller operative to select the value of N based on the frequency of the input signal;
wherein the frequency multiplier is connected to the controller and is operative to multiply by the selected value of N.
18. The circuit of claim 13 , further comprising injection selection circuitry connected to a controller, the injection selection circuitry being operative to connect the input signal to a set of injection points corresponding to the Nth harmonic.
19. The circuit of claim 13 , wherein the frequency multiplier is a variable frequency multiplier.
20. The circuit of claim 13 , further comprising a mixer connected to the frequency-multiplied output, wherein the mixer is operative to mix the input signal with the frequency-multiplied output signal.