IP Library Granted Patent US 9,653,612
Granted Patent B2
US 9,653,612 · App. 14/961,406 · Granted May 16, 2017

Semiconductor device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,653,612
App. No.
14/961,406
Granted
May 16, 2017
Kind
B2
Abstract

A semiconductor device includes a gate electrode having a first side wall at an end thereof, a gate insulating layer on a top surface and the first side wall of the gate electrode, an oxide semiconductor layer facing the first side wall, the gate insulating layer being between the first side wall and the oxide semiconductor layer, a first insulating layer on the oxide semiconductor layer, the oxide semiconductor layer being between the gate insulating layer and the first insulating layer, a first electrode connected with a first portion of the oxide semiconductor layer, and a second electrode connected with a second portion of the oxide semiconductor layer.

Claims (47)

1. A semiconductor device, comprising:

a gate electrode having a first side wall at an end thereof;

a gate insulating layer on a top surface and the first side wall of the gate electrode;

an oxide semiconductor layer facing the first side wall, the gate insulating layer being between the first side wall and the oxide semiconductor layer;

a first insulating layer on the oxide semiconductor layer, the oxide semiconductor layer being between the gate insulating layer and the first insulating layer;

a first electrode connected with a first portion of the oxide semiconductor layer; and

a second electrode connected with a second portion of the oxide semiconductor layer, wherein

the first insulating layer is in contact with the oxide semiconductor layer,

the oxide semiconductor layer is connected with the first electrode via a first opening in the gate insulating layer; and

the second electrode is connected with the oxide semiconductor layer via a second opening in the first insulating layer.

2. The semiconductor device according to claim 1 , wherein the first side wall is tapered.

3. The semiconductor device according to claim 1 , further comprising a second insulating layer between the gate electrode and the first electrode;

wherein the gate electrode overlaps the first electrode as seen in a plan view.

4. The semiconductor device according to claim 3 , wherein:

the second insulating layer has a second side wall at an end thereof;

the gate insulating layer is on the second side wall; and

the oxide semiconductor layer faces the second side wall, and the gate insulating layer is between the second side wall and the oxide semiconductor layer.

5. The semiconductor device according to claim 3 , wherein the first side wall is ring-shaped and is along the end of the gate electrode.

6. The semiconductor device according to claim 3 , wherein the first side wall is inner to the gate electrode, is ring-shaped, and exposed to an opening reaching the first electrode.

7. A semiconductor device, comprising:

a gate electrode having a first side wall at an end thereof;

an oxide semiconductor layer along the first side wall;

a gate insulating layer between the gate electrode and the oxide semiconductor layer;

a first insulating layer on the oxide semiconductor layer, the oxide semiconductor layer being between the gate electrode and the first insulating layer;

a first electrode connected with a first portion of the oxide semiconductor layer; and

a second electrode connected with a second portion of the oxide semiconductor layer, wherein

the first insulating layer is in contact with the oxide semiconductor layer,

the oxide semiconductor layer is connected with the first electrode via a first opening in the gate insulating layer; and

the second electrode is connected with the oxide semiconductor layer via a second opening in the first insulating layer.

8. The semiconductor device according to claim 7 , wherein the first side wall is tapered.

9. The semiconductor device according to claim 7 , further comprising a second insulating layer between the gate electrode and the first electrode;

wherein the gate electrode overlaps the first electrode as seen in a plan view.

10. The semiconductor device according to claim 9 , wherein:

the second insulating layer has a second side wall at an end thereof;

the gate insulating layer is on the second side wall; and

the oxide semiconductor layer faces the second side wall, and the gate insulating layer is between the second side wall and the oxide semiconductor layer.

11. The semiconductor device according to claim 9 , wherein the first side wall is ring-shaped and is along the end of the gate electrode.

12. The semiconductor device according to claim 9 , wherein the first side wall is inner to the gate electrode, is ring-shaped, and exposed to an opening reaching the first electrode.

13. A semiconductor device, comprising:

a gate electrode having a first side wall at an end thereof;

a gate insulating layer on a top surface and the first side wall of the gate electrode;

an oxide semiconductor layer facing the first side wall, the gate insulating layer being between the first side wall and the oxide semiconductor layer;

a first insulating layer on the oxide semiconductor layer, the oxide semiconductor layer being between the gate insulating layer and the first insulating layer;

a first electrode connected with a first portion of the oxide semiconductor layer;

a second electrode connected with a second portion of the oxide semiconductor layer, and

a second insulating layer between the gate electrode and the first electrode;

wherein the gate electrode overlaps the first electrode as seen in a plan view, and the first side wall is inner to the gate electrode, is ring-shaped, and exposed to an opening reaching the first electrode.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 22, 2025
From: JAPAN DISPLAY INC.
To: MAGNOLIA WHITE CORPORATION
Reel/Frame 072130/0313 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2015
From: SASAKI, TOSHINARI
To: JAPAN DISPLAY INC.
Reel/Frame 037227/0639 →