Parameter setting circuit and semiconductor apparatus using the same

1. A parameter setting circuit comprising:

a first parameter setting unit configured to set a first parameter using first code signals generated by adjusting a value of parameter information to conform to a gear-down mode;

a second parameter setting unit configured to generate pre-code signals by adjusting a value of the first code signals to conform to a specification of a second parameter, and set the second parameter using second code signals generated by adjusting a value of the pre-code signals according to a control signal; and

a control section configured to generate the control signal according to whether it is the gear-down mode and whether the value of the first code signals is an odd number.

2. The parameter setting circuit according to claim 1 , wherein the gear-down mode is a mode that uses a divided clock signal generated by internally dividing an external clock signal.

3. The parameter setting circuit according to claim 1 , wherein the first parameter is a write recovery time.

4. The parameter setting circuit according to claim 1 , wherein the second parameter is a read to precharge delay.

5. The parameter setting circuit according to claim 1 , wherein the first parameter setting unit comprises:

a divider configured to output a value that is obtained by dividing the parameter information by a predetermined divisor;

a multiplexer configured to output the first code signals by selecting one between the parameter information and an output signal of the divider according to a gear-down mode signal which defines the gear-down mode; and

a decoder configured to decode the first code signals, and generate a first parameter setting signal for setting the first parameter.

6. The parameter setting circuit according to claim 5 , wherein the parameter information is generated by coding a value of the first parameter.

7. The parameter setting circuit according to claim 1 , wherein the second parameter setting unit comprises:

a divider configured to output, as the pre-code signals, a value that is obtained by dividing the first code signals by a predetermined divisor;

an adder configured to add a predetermined value to the pre-code signals and output a resultant signal;

a multiplexer configured to output the second code signals by selecting one between the pre-code signals and an output of the adder according to the control signal; and

a decoder configured to decode the second code signals and generate a second parameter setting signal for setting the second parameter.

8. The parameter setting circuit according to claim 7 , wherein, in the case where the first code signals have an odd number, the divider outputs, as the pre-code signals, a value that is obtained by subtracting a least significant bit from the first code signals and then dividing by the predetermined divisor.

9. The parameter setting circuit according to claim 1 , wherein the control section outputs the control signal by combining the gear-down mode signal which defines the gear-down mode and a least significant signal bit of the first code signals.

10. The parameter setting circuit according to claim 1 , wherein the control section outputs the control signal by combining the gear-down mode signal which defines the gear-down mode, the least significant signal bit of the first code signals, and a test mode signal.

11. The parameter setting circuit according to claim 1 , wherein the control section comprises a control section configured to generate the control signal according to whether it is the gear-down mode, whether the value of the first code signals is an odd number, and whether it is a preamble mode.

12. The parameter setting circuit according to claim 11 , wherein the control section outputs the control signal by combining the gear-down mode signal which defines the gear-down mode, the least significant signal bit of the first code signals, and a preamble mode signal which defines the preamble mode.

13. The parameter setting circuit according to claim 11 , wherein the control section outputs the control signal by combining the gear-down mode signal which defines the gear-down mode, the least significant signal bit of the first code signals, the preamble mode signal which defines the preamble mode, and the test mode signal.

14. A semiconductor apparatus comprising:

a core block including a cell array, and row paths and column paths for writing data in the cell array or reading out data from the cell array;

a mode register set configured to store parameter information associated with operations of the semiconductor apparatus;

a parameter setting circuit configured to generate, by adjusting parameter information provided from the mode register that is set to conform to a gear-down mode, a first parameter setting signal for setting a first parameter of the semiconductor apparatus and a second parameter setting signal for setting a second parameter of the semiconductor apparatus; and

an input/output control circuit configured to control activation timing of a column path of the core block according to the first parameter setting signal and the second parameter setting signal.

15. The semiconductor apparatus according to claim 14 , wherein the gear-down mode operates based on a divided clock signal which is generated by dividing an external clock signal.

16. The semiconductor apparatus according to claim 14 , wherein the first parameter is a write recovery time.

17. The semiconductor apparatus according to claim 14 , wherein the second parameter is a read to precharge delay.

18. The semiconductor apparatus according to claim 14 , wherein the parameter setting circuit comprises:

a first parameter setting unit configured to set the first parameter by using first code signals which are generated by adjusting a value of parameter information to conform to the gear-down mode;

a second parameter setting unit configured to generate pre-code signals by adjusting a value of the first code signals to conform to a specification of the second parameter, and set the second parameter using second code signals which are generated by adjusting a value of the pre-code signals according to a control signal; and

a control section configured to generate the control signal according to whether it is the gear-down mode and whether the value of the first code signals is an odd number.

19. The semiconductor apparatus according to claim 14 , wherein the parameter setting circuit comprises:

a first parameter setting unit configured to set the first parameter by using first code signals which are generated by adjusting a value of parameter information to conform to the gear-down mode;

a second parameter setting unit configured to generate pre-code signals by adjusting a value of the first code signals to conform to a specification of the second parameter, and set the second parameter using second code signals which are generated by adjusting a value of the pre-code signals according to a control signal; and

a control section configured to generate the control signal according to whether it is the gear-down mode, whether the value of the first code signals is an odd number, and whether it is a preamble mode.

20. The semiconductor apparatus according to claim 14 , wherein the input/output control circuit is configured to control the activation timing of the column path by shifting a column select signal for enabling the column path by a clock cycle corresponding to the first parameter setting signal or the second parameter setting signal.