Optimizing designs of integrated circuits

1. A method for updating an integrated circuit design, the method comprising:

receiving an integrated circuit design;

identifying a driver having a plurality of outputs, the plurality of outputs driving a plurality of loads through a switching matrix;

replicating a portion of the integrated circuit design, the replicated portion having one or more outputs which are equivalent to associated outputs of the portion;

routing connections between the replicated portion and a rest of the integrated circuit design through a second switching matrix; and

determining whether to use the replicated portion or the portion as a source to drive at least one of the plurality of loads;

reducing a root fanout at an entrance to the switch matrix; and

updating the integrated circuit design with the routing connections; and

wherein the routing connections of the integrated circuit design are provided for fabricating an integrated circuit.

2. The method of claim 1 , where the replicated portion is implemented in software.

3. The method of claim 1 , further comprising:

creating one or more connections to connect the replicated portion to the at least one existing element; and

disconnecting the at least one existing element from the driver.

4. The method of claim 1 , further comprising:

prior to replication, mapping one or more sections of the integrated circuit design to a target architecture.

5. The method of claim 4 , wherein the target architecture is an FPGA.

6. The method of claim 1 , further comprising:

tagging the replicated portion as a replicated component having an equivalent output to the driver, the tag enabling faster optimization during layout and routing of the integrated circuit.

7. An integrated circuit implementation comprising:

a plurality of circuit elements, including first portion and a second portion of the plurality of circuit elements, at least one of the plurality of circuit elements needing an improvement in slack;

a replicated portion of the integrated circuit design, the replicated portion having an output which is equivalent to an output of the first portion, and tagged as the replicated portion;

connections between the replicated portion and the second portion of the integrated circuit design; and

the replicated portion to drive at least one circuit element of the second portion of the integrated circuit when testing determines that the replicated portion provides the improvement in the slack;

wherein the replicated portion is deleted when the replicated portion does not provide the improvement in the slack;

wherein the improved integrated circuit design is provided for fabricating an integrated circuit.

8. The design of claim 7 , wherein the first portion comprises a driver, and the replicated portion comprises an equivalent replicated driver.

9. The design of claim 7 , wherein the replicated portion is implemented in software.

10. The design of claim 7 , further comprising:

the connections further to connect a load to the replicated portion, and disconnect the load from the first portion.

11. The design of claim 7 , wherein the integrated circuit design is mapped to a target architecture prior to replicating.

12. The design of claim 7 , further comprising:

a switching matrix to provide the connections to couple the replicated portion to the second portion integrated circuit.

13. The design of claim 7 , wherein the tagging permits the system to identify replicated component as being equivalent to the portion when routing and moving circuit elements around for optimizing the integrated circuit design.

14. A method of designing an integrated circuit comprising:

identify a component driving a plurality of loads through a first switching matrix;

replicating the component;

coupling the replicated component to at least one of the plurality of loads, through a second switching matrix;

removing the at least one of the plurality of loads from the component;

reducing a root fanout at an entrance to the first switch matrix; and

creating an updated integrated circuit design;

wherein the updated integrated circuit design is provided for fabricating an integrated circuit.

15. The method of claim 14 , further comprising:

tagging the replicated component to identify it as equivalent to the component;

wherein the tagging simplifies optimization of the integrated circuit during layout and routing.

16. The method of claim 15 , further comprising:

during placing and routing, automatically determining whether to route a connection to a load from the component or the tagged replicated component.

17. The method of claim 14 , further comprising:

prior to replication, mapping one or more sections of the integrated circuit design to a target architecture.

18. The method of claim 14 , further comprising:

identifying a critical load among the plurality of loads; and

coupling the critical load to the replicated component.

19. The method of claim 14 , further comprising:

placing the replicated component within the integrated circuit;

determining a position of the replicated component and the component with respect to a critical load; and

selecting the replicated component or the component to drive the critical load, based on a position of the components.

20. The method of claim 14 , further comprising:

removing the replication when the replication does not produce an improvement in slack.