IP Library Granted Patent US 9,772,942
Granted Patent B2
US 9,772,942 · App. 14/964,006 · Granted Sep 26, 2017

Committing transaction without first flushing processor cache to non-volatile memory when connected to UPS

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Quick Facts
Patent No.
US 9,772,942
App. No.
14/964,006
Granted
Sep 26, 2017
Kind
B2
Abstract

A computing system includes a processor that has a processor cache built-in, and a non-volatile memory, such as a non-volatile dual-inline memory module (NVDIMM), which is being used as system memory within the computing system. The processor processes a transaction. If the computing system is connected to an uninterruptible power supply (UPS) (and the UPS is connected to a mains power source that is currently providing power), the transaction is committed without first flushing the processor cache to the non-volatile memory. If the computing system is not connected to a UPS (and is connected to a mains power source that is currently providing power), the transaction is not committed until the processor cache has been flushed to the non-volatile memory.

Claims (43)

1. A method comprising:

processing a transaction, by a processor of a computing system, the processor having a processor cache built-in;

in response to determining that the computing system is connected to an uninterruptible power supply (UPS) and in response to determining that the UPS is connected to a mains power source that is currently providing power, committing the transaction, by the processor, without first flushing the processor cache to a non-volatile memory of the computing system that is being used as system memory within the computing system; and

in response to determining that the computing system is not connected to the UPS, flushing the processor cache to the non-volatile memory, by the processor, and after flushing the processor cache, committing the transaction, by the processor.

2. The method of claim 1 , wherein processing the transaction results in at least a portion of transaction processing results remaining in the processor cache and not being stored within the non-volatile memory.

3. The method of claim 1 , further comprising:

in response to determining that the computing system is connected to the UPS and in response to determining that the UPS is connected to the mains power source but that the mains power source is not currently providing power,

flushing the processor cache to the non-volatile memory, by the processor, and after flushing the processor cache, committing the transaction, by the processor.

4. The method of claim 3 , further comprising:

in response to determining that the computing system is connected to the UPS and in response to determining that the UPS is connected to the mains power source but that the mains power source is not currently providing power,

after flushing the processor cache and after committing the transaction, powering down the computing system, by the processor, in a controller manner.

5. The method of claim 1 , wherein the transaction is committed without first flushing the processor cache only when the computing system is connected to the UPS.

6. The method of claim 1 , wherein the non-volatile memory is being used as the system memory within the computing device insofar as the non-volatile memory is not being used in a same manner in which a hard disk drive is used within the computing system.

7. The method of claim 1 , wherein the non-volatile memory is a non-volatile dual-inline memory module (NVDIMM).

8. The method of claim 1 , wherein the UPS has built-in power sufficient to at a minimum flush the processor cache to the non-volatile memory.

9. The method of claim 1 , further comprising:

generating the transaction, by an application program being executed by the processor of the computing system.

10. The method of claim 9 , wherein the application program is one of a database application program and a messaging application program.

11. A system comprising:

a power supply to connect the system to a mains power source with or without an uninterruptible power supply (UPS) being connected between the power supply and the mains power source;

a communication link to connect to the UPS to receive information but not power from the UPS;

a processor having a processor cache built-in;

a non-volatile memory to function as system memory within a computing device; and

an application program to run on the processor and to generate a transaction,

wherein the processor is to:

determine whether the power supply is connected to the UPS, via the communication link;

in response to determining that the power supply is connected to the UPS and in response to determining that the mains power source is currently providing power, commit the transaction without first flushing the processor cache to the non-volatile memory; and

in response to determining that the power supply is not connected to the UPS, flush the processor cache to the non-volatile memory, and only thereafter commit the transaction.

12. The system of claim 11 , wherein the processor is to process the transaction, resulting in at least a portion of transaction processing results remaining in the processor cache and not being stored within the non-volatile memory.

13. The system of claim 11 , wherein the processor is further to:

in response to determining that the power supply is connected to the UPS and in response to determining that the mains power source is not currently providing power,

flush the processor cache to the non-volatile memory, and only thereafter commit the transaction.

14. The system of claim 13 , wherein the processor is further to:

in response to determining that the power supply is connected to the UPS and in response to determining that the mains power source is not currently providing power,

after flushing the processor cache and after committing the transaction, power down the computing system in a controller manner.

15. A non-transitory computer-readable data storage medium storing computer-executable code that is executable by a processor having a processor cache built-in to perform a method comprising:

processing a transaction;

in response to determining that a computing system including the processor is connected to an uninterruptible power supply (UPS) and that the UPS is connected to a mains power source that is currently providing power, committing the transaction without first flushing the processor cache to a non-volatile memory of the computing system that is being used as system memory within the computing system; and

in response to determining that the computing system is not connected to the UPS and is connected to the mains power source that is currently providing power, flushing the processor cache to the non-volatile memory, and only after flushing the processor cache, committing the transaction.

16. The non-transitory computer-readable data storage medium of claim 15 , wherein processing the transaction results in at least a portion of transaction processing results remaining in the processor cache and not being stored within the non-volatile memory.

17. The non-transitory computer-readable data storage medium of claim 15 , wherein the method further comprises:

in response to determining that the computing system is connected to the UPS and in response to determining that the UPS is connected to the mains power source but that the mains power source is not currently providing power,

flushing the processor cache to the non-volatile memory, and only after flushing the processor cache, committing the transaction.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2025
From: LENOVO GLOBAL TECHNOLOGIES INTERNATIONAL LIMITED
To: LENOVO GLOBAL TECHNOLOGIES SWITZERLAND INTERNATIONAL GMBH
Reel/Frame 069869/0614 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2019
From: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE LTD.
To: LENOVO GLOBAL TECHNOLOGIES INTERNATIONAL LTD
Reel/Frame 050304/0861 →
CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF ASSIGNEE PREVIOUSLY RECORDED ON REEL 037251 FRAME 0209. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 10, 2015
From: BAHALI, SUMANTA KUMAR; LANGGOOD, JOHN K.; REINBERG, KEVIN MICHAEL; VERNON, KEVIN S.
To: LENOVO ENTERPRISE SOLUTIONS (SINGAPORE) PTE. LTD.
Reel/Frame 037268/0199 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 9, 2015
From: BAHALI, SUMANTA KUMAR; LANGGOOD, JOHN K.; REINBERG, KEVIN MICHAEL; VERNON, KEVIN S.
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 037251/0209 →