Semiconductor storage device and control method of semiconductor storage device with detecting levels of a multi-ary signal

1. A semiconductor storage device, comprising:

N word lines, N being an integer of four or greater;

M bit lines that intersect with the word lines, M being an integer of two or greater;

multiple memory cells placed at positions where the word lines and the bit lines intersect, the memory cell storing binary data; and

a read circuit connected to the M bit lines, the read circuit detecting levels of a multi-ary signal,

wherein the read circuit detects levels of a quarternary signal on a bit line selected from the M bit lines, and

the semiconductor storage device performs an error operation if data based on the detection results for signal levels is determined to be incorrect.

2. The semiconductor storage device according to claim 1 , wherein

each of the multiple memory cells has a variable resistance element that transitions between a high resistance state and a low resistance state.

3. A semiconductor storage device, comprising:

N word lines, N being an integer of four or greater;

M bit lines that intersect with the word lines, M being an integer of two or greater;

multiple memory cells placed at positions where the word lines and the bit lines intersect, the memory cell storing binary data; and

a read circuit connected to the M bit lines, the read circuit detects levels of a multi-ary signal, wherein the read circuit has M sense amplifiers corresponding to the M bit lines, and

wherein each of the sense amplifiers has:

a current mirror circuit group connected to the bit line; and

three detection circuits connected to the current mirror circuit group that detect different signal levels, and

the semiconductor storage device performs an error operation if data based on the detection results for signal levels is determined to be incorrect.

4. The semiconductor storage device according to claim 3 , wherein

each of the detection circuits has:

an input node connected to the current mirror circuit group;

a capacitance element electrically connected at one end to the input node and an output node; and

a current source connected to the input node, and

wherein the three detection circuits are different in drive capability of the current source.

5. The semiconductor storage device according to claim 3 , wherein

each of the detection circuits has:

an input node connected to the current mirror circuit group;

a current source connected to the input node; and

a comparator that compares the potential on the input node and a reference potential to output the comparing result onto an output node, and

wherein the three detection circuits are equivalent in drive capability of the current source and are supplied with reference potentials of different levels.

6. The semiconductor storage device according to claim 3 , wherein

each of the multiple memory cells has a variable resistance element that transitions between a high resistance state and a low resistance state.

7. A semiconductor storage device comprising:

N word lines, N being an integer of four or greater;

M bit lines that intersect with the word lines, M being an integer of two or greater;

multiple memory cells placed at positions where the word lines and the bit lines intersect, the memory cell storing binary data; and

a read circuit connected to the M bit lines, the read circuit detecting levels of a multi-ary signal,

wherein the read circuit detects three times the level of the signal from four memory cells, as candidates for selection, on a bit line selected from the M bit lines, and

the semiconductor storage device performs an error operation if data based on the detection results for signal levels is determined to be incorrect.

8. The semiconductor storage device according to claim 7 , further comprising a control circuit that selects three word lines in parallel,

wherein the read circuit detects the level of the signal output from three selected memory cells on the selected bit line with three word lines being selected by the control circuit.

9. The semiconductor storage device according to claim 7 , further comprising a control circuit that selects three word lines in parallel,

wherein the control circuit determines four word lines from among the N word lines to be candidates for selection and performs selection operation of three word lines from among the four word lines three times such that a non-selected word line is different for the three times, and

wherein the read circuit detects the level of the signal output from three memory cells selected from among the four memory cells three times while the non-selected memory cell is different for the three times.

10. The semiconductor storage device according to claim 9 , wherein

in selection operations of the three times, the control circuit selects one of the four word lines fixedly and selects four word lines from remaining three word lines.

11. The semiconductor storage device according to claim 9 , wherein

the control circuit has N decoding circuits corresponding to the N word lines, and

wherein each of the decoding circuits has:

four sub-decoding circuits corresponding to the four word lines as candidates for selection; and

a combining circuit that combines signals output from the four sub-decoding circuits.

12. The semiconductor storage device according to claim 11 , wherein

each of the four sub-decoding circuits decodes a combination of address signals and a control signal to decide on the non-selected word line.

13. The semiconductor storage device according to claim 7 , further comprising:

a hold circuit that holds detection results for the signal levels of the K times; and

a recovery circuit that recovers data of the four memory cells based on the detection results for signal levels of the three times.

14. The semiconductor storage device according to claim 13 , wherein

the recovery circuit converts a combination of the three times of the signal level into four-bit data to recover data of the four memory cells.

15. The semiconductor storage device according to claim 7 , wherein

each of the multiple memory cells has a variable resistance element that transitions between a high resistance state and a low resistance state.

16. A control method of a semiconductor storage device which has N word lines, M bit lines that intersect with the word lines, and multiple memory cells placed at positions where the word lines and the bit lines intersect, N being an integer of four or greater, M being an integer of two or greater, the memory cell storing binary data, the control method comprising:

selecting three word lines in parallel from among the N word lines;

detecting a level of a multi-ary signal output from three selected memory cells on one bit line selected from among the M bit lines in a state where the three word lines are selected; and

performing an error operation if data based on the detection results for signal levels is determined to be incorrect.

17. The control method of the semiconductor storage device according to claim 16 , wherein

the selecting includes determining four word lines from among the N word lines to be candidates for selection and performing selection operation of three word lines from among the four word lines three times such that a non-selected word line is different for the three times, and

wherein the detecting includes detecting the level of the signal output from three memory cells selected from among the four memory cells three times while the non-selected memory cell is different for the three times.

18. The control method of the semiconductor storage device according to claim 17 , wherein

the selecting includes, in selection operations of the three times, selecting one of the four word lines fixedly and selecting two word lines from remaining three word lines.

19. The control method of the semiconductor storage device according to claim 18 , further comprising:

holding detection results for signal levels of the three times; and

recovering data of the four memory cells based on the detection results for signal levels of the three times.

20. The semiconductor storage device according to claim 16 , wherein

each of the multiple memory cells has a variable resistance element that transitions between a high resistance state and a low resistance state.