Image sensor with hybrid heterostructure
View Patent ↗An image sensor architecture provides an SNR in excess of 100 dB, without requiring the use of a mechanical shutter. The circuit components for an active pixel sensor array are separated and arranged vertically in at least two different layers in a hybrid chip structure. The top layer is preferably manufactured using a low-noise PMOS manufacturing process, and includes the photodiode and amplifier circuitry for each pixel. A bottom layer is preferably manufactured using a standard CMOS process, and includes the NMOS pixel circuit components and any digital circuitry required for signal processing. By forming the top layer in a PMOS process optimized for forming low-noise pixels, the pixel performance can be greatly improved, compared to using CMOS. In addition, since the digital circuitry is now separated from the imaging circuitry, it can be formed using a standard CMOS process, which has been optimized for circuit speed and manufacturing cost. By combining the two layers into a stacked structure, the top layer (and any intermediate layer(s)) acts to optically shield the lower layer, thereby allowing charge to be stored and shielded without the need for a mechanical shutter.
1. An image sensor comprising:
a first CMOS circuit layer comprising an array of pixel elements;
each pixel element comprising:
a photodiode; and
an amplifier; and
first Analog to Digital Converter (ADC) circuit portions;
a second CMOS layer comprsing:
supporting pixel circuitry, including a global shutter sample and hold circuit; and
second Analog to Digital Converter (ADC) circuit portions connected to corresponding first ADC circuit portions in the first CMOS layer; and
a blocking layer formed between the first CMOS layer and the second CMOS layer.
2. The image sensor of claim 1 , wherein the supporting pixel circuitry in the second CMOS layer comprises a signal storage capacitor for each pixel, each signal storage capacitor is optically shielded by the blocking layer.
3. The image sensor of claim 1 , wherein the blocking layer comprises a plurality of capacitors, wherein a capacitor is electrically connected to a pixel element in the first CMOS layer, and supporting pixel circuitry in the second CMOS layer.
4. The image sensor of claim 1 , wherein the blocking layer is a metal layer formed as part of either the first CMOS layer or the second CMOS layer.
5. The image sensor of claim 1 , wherein the blocking layer is a metal layer formed partially in both the first CMOS layer and the second CMOS layer.
6. The image sensor of claim 1 , wherein the layers are bonded using Wafer on Wafer (WoW) bonding.
7. The image sensor of claim 1 further comprising a correlated double sampling (CDS) circuit comprising:
a correlated double sampling capacitor formed in the blocking layer; and
correlated double sampling circuitry formed in the second CMOS layer.
8. The image sensor of claim 1 , wherein the sample and hold circuit comprises a trench capacitor formed in the second CMOS layer.
9. An image sensor comprising:
a first CMOS circuit layer comprising an array of pixel elements;
each pixel element comprising:
a photodiode; and
an amplifier; and
first Column Buffer circuit portions;
a second CMOS layer comprising:
supporting pixel circuitry, including a global shutter sample and hold circuit; and
second Column Buffer circuit portions connected to corresponding first Column Buffer circuit portions in the first CMOS layer; and
a blocking layer formed between the first CMOS layer and the second CMOS layer.
10. The image sensor of claim 9 , wherein the supporting pixel circuitry in the second CMOS layer comprises a signal storage capacitor for each pixel, each signal storage capacitor is optically shielded by the blocking layer.
11. The image sensor of claim 9 , wherein the blocking layer comprises a plurality of capacitors, wherein a capacitor is electrically connected to a pixel element in the first CMOS layer, and supporting pixel circuitry in the second CMOS layer.
12. The image sensor of claim 9 , wherein the blocking layer is a metal layer formed as part of either the first CMOS layer or the second CMOS layer.
13. The image sensor of claim 9 , wherein the blocking layer is a metal layer formed partially in both the first CMOS layer and the second CMOS layer.
14. The image sensor of claim 9 , wherein the layers are bonded using Wafer on Wafer (WoW) bonding.
15. The image sensor of claim 9 further comprising a correlated double sampling (CDS) circuit comprising:
a correlated double sampling capacitor formed in the blocking layer; and
correlated double sampling circuitry formed in the second CMOS layer.
16. The image sensor of claim 9 , wherein the sample and hold circuit comprises a trench capacitor formed in the second CMOS layer.