TECHNIQUES TO BOOST WORD-LINE VOLTAGE USING PARASITIC CAPACITANCES
A memory device with word-line voltage boosting includes a set of first switches that are operable to couple a word-line of the memory device to a supply voltage to pull the word-line up to a rail voltage. A dummy line including a conductive route can be disposed in a vicinity of the word-line to form a parasitic coupling capacitance with the word-line. A second switch is operable to couple the dummy line to the supply voltage to pull the dummy line to the rail voltage. Pulling up the dummy line boosts the word-line voltage above the rail voltage by a boost voltage.
1 . A memory device with word-line voltage boosting, the memory device comprising:
a plurality of switches operable to couple a word-line of the memory device to a supply voltage to pull the word-line up to a rail voltage; and
a dummy line forming a parasitic coupling capacitance with the word-line, the parasitic coupling capacitance to be charged to the rail voltage to boost the word-line voltage by a boost voltage,
wherein the boost voltage is controllable by varying a count of closed switches of the plurality of switches.
2 . The memory device of claim 1 , wherein charging the parasitic coupling capacitance to boost the word-line voltage of the memory device is performed during a memory read or write operation to assist the read or write operation.
3 . The memory device of claim 1 , wherein the dummy line is to be pre-discharged to ground potential prior to a memory read or write operation.
4 . The memory device of claim 1 , wherein the word-line is to be decoupled from the supply voltage prior to charging the parasitic coupling capacitance to the rail voltage.
5 . The memory device of claim 4 , further comprising a controller to operate the plurality of switches to perform coupling and decoupling of the word-line to and from the supply voltage.
6 . The memory device of claim 5 , wherein the plurality of switches are implemented by using PMOS transistors including gate-drain parasitic capacitances, and the gate-drain parasitic capacitances of the PMOS transistors are to allow further boosting of the word-line voltage by leveraging a low-to-high voltage transition of the gate-drain parasitic capacitances.
7 . The memory device of claim 5 , further comprising a dummy line switch operable to couple the dummy line to the supply voltage to pull the dummy line to the rail voltage.
8 . The memory device of claim 7 , wherein the boost voltage is controllable by changing a time duration that the dummy line switch is kept closed.
9 . The memory device of claim 1 , wherein the memory device comprises a ternary content-addressable memory (TCAM), wherein the dummy line comprises a match line of the TCAM.
10 . The memory device of claim 1 , wherein the memory device comprises a static random-access memory (SRAM), and wherein the dummy line comprises a shield line running in parallel to the word-line of the SRAM.
11 . A memory device comprising:
a word-line to be coupled to a supply voltage to pull the word-line up to a rail voltage;
a dummy line forming a parasitic coupling capacitance with the word-line; and
a first switch operable to be closed for a variable time duration to couple the dummy line to the supply voltage to boost a voltage of the word-line by a first voltage through charging the parasitic coupling capacitance,
wherein the first voltage is controllable by varying the time duration.
12 . The memory device of claim 11 , further comprising a controller to operate the first switch to couple the dummy line to the supply voltage prior to initiating a read or write operation of the memory device.
13 . The memory device of claim 11 , further comprising a second switch operable to pre-discharge the dummy line to ground potential, and a controller to operate the second switch to pre-discharge the dummy line to ground potential prior to initiating a memory read or write operation.
14 . The memory device of claim 11 , further comprising a plurality of switches operable to couple the word-line to the supply voltage, and a controller to operate the plurality of switches to decouple the word-line from the supply voltage prior to operating the first switch to couple the dummy line to the supply voltage.
15 . The memory device of claim 14 , wherein the plurality of switches are implemented by using PMOS transistors including gate-drain parasitic capacitances, and wherein a low-to-high voltage transition of the gate-drain parasitic capacitances of the PMOS transistors are leveraged to further boost the word-line voltage.
16 . The memory device of claim 15 , wherein the controller is to change the boost voltage by changing a count of closed switches of the plurality of switches used to couple the word-line to the supply voltage.
17 . The memory device of claim 10 , wherein the dummy line comprises a match line if the memory device comprises a ternary content-addressable memory (TCAM) or a shield line running in parallel to the word-line if the memory device comprises a static random-access memory (SRAM).
18 . A communication device, comprising:
a memory device comprising:
a word-line;
a dummy line disposed in a vicinity of the word-line; and
a plurality of switches operable to couple the word-line to a supply voltage to pull the word-line up to a rail voltage,
wherein:
the dummy line forms a parasitic coupling capacitance with the word-line, the parasitic coupling capacitance is to boost the word-line voltage by a boost voltage upon charging to the rail voltage, and
the boost voltage is controllable by selectively closing a number of switches of the plurality of switches.
19 . The communication device of claim 18 , wherein the memory device comprises a ternary content-addressable memory (TCAM) or a static random-access memory (SRAM).
20 . The communication device of claim 18 , wherein the memory device further comprises a controller configured to operate the plurality of switches and a dummy line switch, wherein the dummy line switch is operable to couple the parasitic coupling capacitance to the supply voltage, and wherein the controller is to control the boost voltage by changing a time duration that the dummy line switch is kept closed.