Memory system and operating method thereof
View Patent ↗A memory system includes a memory device of lower read operation speed; a memory cache of higher read operation speed; and a controller suitable for: setting one of access patterns to the memory device defined by pairs of former and latter addresses provided to the memory system within a set input time interval as a prefetch pattern; performing a prefetch operation of caching data corresponding to the latter address from the memory device to the memory cache according to the prefetch pattern; and reading the cached data from the memory cache in response to a read command provided with the latter address of the prefetch pattern.
1. A memory system, comprising:
a memory device of lower read operation speed;
a memory cache of higher read operation speed; and
a controller configured to:
set at least one access pattern to the memory device defined by a pair of former and latter addresses provided to the memory system within a set input time interval as a prefetch pattern;
perform a prefetch operation including caching data corresponding to the latter address from the memory device to the memory cache according to the prefetch pattern; and
read the cached data from the memory cache in response to a read command provided with the latter address of the prefetch pattern,
wherein the prefetch pattern includes information denoting a number of access operations performed according to the former address that is greater than a reference number.
2. The memory system of claim 1 , wherein the access operation performed according to the former address is a program or a read operation.
3. The memory system of claim 2 , wherein each of the number of access operations performed according to the former address is followed by a read operation performed according to the latter address.
4. The memory system of claim 1 , wherein the controller performs the prefetch operation in case of performing an access operation according to the former address of the prefetch pattern.
5. The memory system of claim 1 , wherein the controller further stores the prefetch pattern in a page buffer of the memory device.
6. The memory system of claim 5 , wherein the controller stores the prefetch pattern according to a weighted value of the prefetch pattern.
7. The memory system of claim 6 , the weighted value of the prefetch pattern is determined on the basis of input frequency of the prefetch pattern.
8. The memory system of claim 6 , the weighted value of the prefetch pattern is determined on the basis of input recency of the prefetch pattern.
9. The memory system of claim 5 , wherein the controller further removes from the memory cache the prefetch pattern and the corresponding cached data, which are not provided during a predetermined amount of time.
10. An operating method of a memory system comprising a memory device of lower read operation speed and a memory cache of higher read operation speed, the method comprising:
setting at least one access pattern to the memory device defined by pairs of former and latter addresses provided to the memory system within a set input time interval as a prefetch pattern;
performing a prefetch operation including caching data corresponding to the latter address from the memory device to the memory cache according to the prefetch pattern; and
reading the cached data from the memory cache in response to a read command provided with the latter address of the prefetch pattern,
wherein the prefetch pattern includes information of a number of access operations performed according to the former address greater than a reference number.
11. The method of claim 10 , wherein the access operation performed according to the former address is one of program and read operations.
12. The method of claim 11 , wherein each of the number of access operations performed according to the former address is followed by a read operation performed according to the latter address.
13. The method of claim 10 , wherein the prefetch operation is performed in case of performing an access operation according to the former address of the prefetch pattern.
14. The method of claim 10 , further comprising storing the prefetch pattern in a page buffer of the memory device.
15. The method of claim 14 , wherein the storing of the prefetch pattern is performed according to a weighted value of the prefetch pattern.
16. The method of claim 15 , the weighted value of the prefetch pattern is determined on the basis of input frequency of the prefetch pattern.
17. The method of claim 15 , the weighted value of the prefetch pattern is determined on the basis of input recency of the prefetch pattern.
18. The method of claim 14 , further comprising removing from the memory cache the prefetch pattern and the corresponding cached data, which are not provided during a predetermined amount of time.