Signature-based sleep recovery operation flow
The present disclosure describes methods and apparatus for implementing a signature-based sleep recovery operation flow for booting a system-on-chip (SoC). When the SoC begins its normal boot flow, a controller retrieves a sleep recovery signature from a register and compares the retrieved sleep recovery signature to a default signature. If the sleep recovery signature matches the default signature, the SoC enters a ROM checksum fail debug flow and, upon satisfying the requirements of the ROM checksum fail debug flow, enters a sleep recovery boot flow, which restores the SoC to the operational state it was in prior to entering the sleep mode. If the sleep recovery signature does not match the default signature, the SoC continues with the normal boot flow or, by use of external pins, can be forced into a normal debug mode flow so that the boot code can be debugged.
1. A method for booting a system-on-chip (SoC), the method comprising:
retrieving a sleep recovery signature from a register of the SoC, the sleep recovery signature having been set in the register of the SoC prior to the SoC entering the sleep mode;
comparing the sleep recovery signature to a default signature;
entering, responsive to the sleep recovery signature matching the default signature, a ROM checksum fail debug flow; and
entering, responsive to the sleep recovery signature not matching the default signature, a normal debug mode flow.
2. The method of claim 1 , the ROM checksum fail debug flow further comprising:
performing a checksum operation on a ROM of a first central processing unit (CPU);
determining whether the checksum operation on the ROM of the first CPU fails;
responsive to the checksum operation on the ROM of the first CPU failing, entering an infinite loop; and
responsive to the checksum operation on the ROM of the first CPU not failing, performing a checksum operation on a ROM of an additional CPU.
3. The method of claim 2 , further comprising, for each additional CPU:
determining whether the checksum operation on the ROM of the additional CPU fails;
responsive to the checksum operation on the ROM of the additional CPU failing, entering an infinite loop.
4. The method of claim 3 , further comprising, responsive to the checksum operation on the ROM of the additional CPU not failing:
determining whether to enter a sleep recovery boot flow;
responsive to determining not to enter the sleep recovery boot flow, completing a normal boot flow to enter a fully functional state; and
responsive to determining to enter the sleep recovery boot flow, completing sleep recovery operations that restore the SoC to an operational state that corresponds to an operational state that existed when the SoC entered the sleep mode.
5. The method of claim 4 , the determining whether to enter a sleep recovery boot flow further comprising determining to enter the sleep recovery boot flow responsive to the sleep recovery signature matching the default signature.
6. The method of claim 1 , the register further comprising a stack of multiple always on (AON) registers.
7. The method of claim 1 , the normal debug mode flow further comprising:
determining whether a first check mode operation has been activated via a first external pin;
responsive to determining that the first check mode operation has been activated, continuing the normal debug mode flow;
responsive to determining that the first check mode operation has not been activated, entering the ROM checksum fail debug flow;
the continuing the normal debug mode flow including determining whether a second check mode operation has been activated via a second external pin; and
responsive to determining that the second check mode operation has been activated, downloading a boot code for booting the SoC to a memory that is external to the SoC.
8. The method of claim 7 , further comprising:
responsive to determining that the second check mode operation has not been activated, entering into an infinite loop displaying an error notification.
9. The method of claim 7 , the first and second external pins comprising general purpose input/output (GPIO) pins.
10. A System-on-Chip (SoC), comprising:
a register; and
a controller with a signature comparison module configured to set a signature in the register prior to the SoC entering a sleep mode, and to, when recovering from the sleep mode:
retrieve a sleep recovery signature from the register;
compare the sleep recovery signature to a default signature;
enter, responsive to the sleep recovery signature matching the default signature, a ROM checksum fail debug flow; and
enter, responsive to the sleep recovery signature not matching the default signature, a normal debug mode flow.
11. The SoC of claim 10 , the ROM checksum fail debug flow further comprising:
performing a checksum operation on a ROM of a first central processing unit (CPU):
determining whether the checksum operation on the ROM of the first CPU fails;
responsive to the checksum operation on the ROM of the first CPU failing, entering an infinite loop; and
responsive to the checksum operation on the ROM of the first CPU not failing, performing a checksum operation on a ROM of an additional CPU.
12. The SoC of claim 11 , the ROM checksum fail debug flow further comprising, for each additional CPU:
determining whether the checksum operation on the ROM of the additional CPU fails;
responsive to the checksum operation on the ROM of the additional CPU failing, entering an infinite loop.
13. The SoC of claim 12 , the ROM checksum fail debug flow further comprising, responsive to the checksum operation on the ROM of the additional CPU not failing:
determining whether to enter a sleep recovery boot flow;
responsive to determining not to enter the sleep recovery boot flow, completing a normal boot flow to enter a fully functional state; and
responsive to determining to enter the sleep recovery boot flow, completing sleep recovery operations that restore the SoC to an operational state that corresponds to an operational state that existed when the SoC entered the sleep mode.
14. The SoC of claim 13 , the determining whether to enter a sleep recovery boot flow further comprising determining to enter the sleep recovery boot flow responsive to the sleep recovery signature matching the default signature.
15. The SoC of claim 10 , the register comprising a stack of multiple always on (AON) registers.
16. The SoC of claim 10 , the normal debug flow mode further comprising:
determining whether a first check mode operation has been activated via a first external pin of the SoC;
responsive to determining that the first check mode operation has been activated, continuing the normal debug mode flow;
responsive to determining that the first check mode operation has not been activated, entering the ROM checksum fail debug flow;
the continuing the normal debug mode flow including determining whether a second check mode operation has been activated via a second external pin of the SoC; and
responsive to determining that the second check mode operation has been activated, downloading, to a memory that is external to the SoC, a boot code for booting the SoC.
17. The SoC of claim 16 , further comprising:
responsive to determining that the second check mode operation has not been activated, entering into an infinite loop displaying an error notification.
18. A device comprising:
a boot read only memory (ROM);
a memory; and
a system-on-chip (SoC), the SoC comprising:
a register; and
a controller configured to set a signature in the register prior to the SoC entering a sleep mode, and to, when recovering from the sleep mode:
retrieve a sleep recovery signature from the register;
compare the sleep recovery signature to a default signature;
enter, responsive the sleep recovery signature matching the default signature, a ROM checksum fail debug flow; and
enter, responsive to the sleep recovery signature not matching the default signature, a normal debug mode flow.
19. The device of claim 18 , the device further comprising a first central processing unit (CPU) and an additional CPU, the ROM checksum fail debug flow further comprising:
performing a checksum operation on a ROM of the first CPU;
determining whether the checksum operation on the ROM of the first CPU fails;
responsive to the checksum operation on the ROM of the first CPU failing, entering an infinite loop;
responsive to the checksum operation on the ROM of the first CPU not failing, performing a checksum operation on a ROM of the additional CPU;
determining whether the checksum operation on the ROM of the additional CPU fails;
responsive to the checksum operation on the ROM of the additional CPU failing, entering an infinite loop;
responsive to the checksum operation on the ROM of the additional CPU not failing:
determining whether to enter a sleep recovery boot flow;
responsive to determining not to enter the sleep recovery boot flow, completing a normal boot flow to enter a fully functional state;
responsive to determining to enter the sleep recovery boot flow, completing sleep recovery operations that restore the SoC to an operational state that corresponds to an operational state that existed when the SoC entered the sleep mode.
20. The device of claim 18 , the normal debug mode flow further comprising:
determining whether a first check mode operation has been activated via a first external pin of the SoC;
responsive to determining that the first check mode operation has been activated, continuing the normal debug mode flow;
responsive to determining that the first check mode operation has not been activated, entering the ROM checksum fail debug flow;
the continuing the normal debug mode flow including determining whether a second check mode operation has been activated via a second external pin of the SoC; and
responsive to determining that the second check mode operation has been activated, downloading, to a memory that is external to the SoC, a boot code for booting the SoC.