IP Library Granted Patent US 9,742,219
Granted Patent B2
US 9,742,219 · App. 14/970,329 · Granted Aug 22, 2017

Circuit for comparing a voltage with a threshold

Inventors: Jérôme Willemin (Tullins, FR); Sébastien Boisseau (Grenoble, FR); Séverin Trochut (Gilly sur Isere, FR); Stéphane Monfray (Eybens, FR)
Assignees: Commissariat à l'Énergie Atomique et aux Énergies Alternatives; STMicroelectronics SA
H02J7/345G01R19/0084G01R19/16519G01R19/16538G01R19/16576H02M3/156H02N2/181H03K3/021H03K3/2893H03K3/3565H03K17/302H02M2001/0022H03K2217/0036
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Quick Facts
Patent No.
US 9,742,219
App. No.
14/970,329
Granted
Aug 22, 2017
Kind
B2
Abstract

A circuit for comparing a voltage with a threshold, including: first and second nodes of application of the voltage; a first branch including a first transistor series-connected with a first resistor between first and second nodes; a second branch parallel to the first branch, including second and third series-connected resistors forming a voltage dividing bridge between the first and second nodes, the midpoint of the dividing bridge being connected to a control node of the first transistor; and a third branch including a second transistor in series with a resistive and/or capacitive element, between the control node of the first transistor and the first or second node, a control node of the second transistor being connected to the junction point of the first transistor and of the first resistor.

Claims (32)

1. A circuit for comparing a voltage with a threshold, comprising:

first and second nodes of application of said voltage;

a first branch comprising a first transistor coupled in series with a first resistor between the first and second nodes;

a second branch parallel to the first branch, comprising second and third resistors coupled in series forming a voltage dividing bridge between the first and second nodes, the midpoint of the dividing bridge being coupled to a control node of the first transistor; and

a third branch comprising: a second transistor having its conduction nodes respectively coupled to the first or second node and to a third node, and having a control node coupled to the junction point of the first transistor and of the first resistor; and a resistor or a capacitor or a series or parallel association of a resistor and of a capacitor, having its ends respectively coupled to the third node and to the control node of the first transistor.

2. The circuit of claim 1 , wherein the third node and the first or second node of application of said voltage not coupled to the third branch form nodes for providing an output voltage of the circuit, intended to be coupled to a load to be powered.

3. The circuit of claim 1 , further comprising:

between the third node and the first or second node of application of said voltage not coupled to the third branch, a fourth resistor; and

between the first or second node of application of said voltage not coupled to the third branch and a fourth node, a third transistor having a control node coupled to the third node,

wherein the first or second node of application of said voltage coupled to the third branch and the fourth node form nodes for providing an output voltage of the circuit, intended to be coupled to a load to be powered.

4. The circuit of claim 1 , wherein:

the first transistor is an NPN bipolar transistor or an N-channel MOS transistor;

the second transistor is a P-channel MOS transistor or a PNP bipolar transistor;

in the first branch, the first resistor is on the side of the first node and the first transistor is on the side of the second node; and

the third branch is located between the control node of the first transistor and the first node.

5. The circuit of claim 1 , wherein:

the first transistor is a PNP bipolar transistor or a P-channel MOS transistor;

the second transistor is an N-channel MOS transistor or an NPN bipolar transistor;

in the first branch, the first resistor is on the side of the second node and the first transistor is on the side of the first node; and

the third branch is located between the control node of the first transistor and the second node.

6. The circuit of claim 1 , wherein the resistor or the capacitor or the series or parallel association of a resistor and of a capacitor is a resistor.

7. The circuit of claim 1 , wherein the resistor or the capacitor or the series or parallel association of a resistor and of a capacitor is a series or parallel association of a resistor and of a capacitor.

8. The circuit of claim 1 , wherein at least one of the second and third resistors is a thermistor or an association of one or a plurality of resistors and of one or a plurality of thermistors.

9. An ambient energy harvesting generator, comprising:

an element for converting ambient energy into electrical energy;

a first capacitor capable of storing charges generated by said conversion element; and

a first comparison circuit of claim 1 , the first capacitor being coupled between the first and second nodes of the first comparison circuit.

10. The generator of claim 9 , further comprising a circuit for inductively charging a second capacitor from the input voltage and the first comparison circuit.

11. The generator of claim 10 , wherein the inductive charge circuit is a voltage step-down circuit.

12. The generator of claim 10 , wherein the inductive charge circuit is a voltage step-up circuit.

13. The generator of claim 10 , further comprising a second comparison circuit of claim 1 , the second capacitor being coupled between the first and second nodes of the second comparison circuit.

14. The generator of claim 9 , further comprising a diode, a transistor, and an electric booster battery coupled in series between the terminals of the first capacitor.

Assignments (4)
CHANGE OF NAME Recorded Jan 21, 2024
From: STMICROELECTRONICS SA
To: STMICROELECTRONICS FRANCE
Reel/Frame 066357/0693 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2016
From: WILLEMIN, JÉRÔME; BOISSEAU, SÉBASTIEN
To: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
Reel/Frame 040252/0919 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2016
From: TROCHUT, SÉVERIN
To: STMICROELECTRONICS SA
Reel/Frame 040252/0988 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 8, 2016
From: MONFRAY, STÉPHANE
To: STMICROELECTRONICS (CROLLES 2) SAS
Reel/Frame 040253/0066 →
Priority Claims (1)
FR 14 62427 · Dec 15, 2014 · national
Continuity (1)
Related Publication 20160172898A1 · Jun 16, 2016