Method of configuring memory cells in a solid state drive based on read/write activity and controller therefor
View Patent ↗A solid-state storage device (SSD) controller is provided for use with an SSD. The SSD includes a plurality of memory cells, such as non-volatile memory (NVM) cells. The SSD controller comprises a processor and a memory storing statements and instructions for execution by the processor to perform a method of configuring the memory cells. In a dynamic configuration implementation in which at least a subset of the NVM cells are configured in a first bit retention mode, the method includes: monitoring data activity in relation to the SSD; and dynamically reconfiguring the subset of the NVM cells in a second bit retention mode based on the monitored data activity, such as whether data traffic comprises a majority of read activity or write activity. In a static configuration implementation, the method includes receiving at least one performance characteristic for the NVM cells; and configuring the subset of the NVM cells in a first bit retention mode based on the received at least one performance characteristic.
1. A solid-state storage device (SSD) controller for use with an SSD, the SSD including a plurality of non-volatile memory (NVM) cells, at least a subset of the plurality of NVM cells being configured in a first bit retention mode, the plurality of NVM cells each being configurable to operate in a plurality of bit retention modes, each of the plurality of NVM storage bit retention modes enabling storage of one or more bits of information in the plurality of NVM cells, the SSD controller comprising:
a processor; and
a memory storing statements and instructions for execution by the processor to:
monitor data traffic patterns into and out of the SSD;
determine, based on the monitored data traffic patterns into and out of the SSD, whether the data traffic comprises a majority of read activity or a majority of write activity;
dynamically reconfigure the subset of the plurality of NVM cells to operate in a second bit retention mode based on the monitored traffic patterns, the second bit retention mode being different from the first bit retention mode, by:
when the first bit retention mode of the subset of the plurality of NVM cells is a single-level cell (SLC) mode or a multi-level cell (MLC) mode, reconfiguring the subset of the plurality of NVM cells to operate in a triple-level cell (TLC) mode if the monitored traffic patterns are determined to comprise a majority of read activity; and
when the first bit retention mode of the subset of the plurality of NVM cells is a quad-level cell (QLC) mode or a TLC mode, reconfiguring the subset of the plurality of NVM cells to operate in the SLC mode or the MLC mode if the monitored traffic patterns are determined to comprise a majority of write activity.
2. The SSD controller of claim 1 wherein the plurality of NVM cells comprise NAND flash memory cells.
3. The SSD controller of claim 1 wherein reconfiguring the subset of the plurality of NVM cells to operate in the SLC mode or the MLC mode comprises reconfiguring the subset of the NVM cells from the QLC mode or the TLC mode to the MLC mode.
4. The SSD controller of claim 1 wherein the monitored data traffic patterns comprise data traffic patterns of data provided by a host in communication with the SSD.