IP Library Granted Patent US 9,989,592
Granted Patent B2
US 9,989,592 · App. 14/975,685 · Granted Jun 5, 2018

Interfaces for wireless debugging

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Quick Facts
Patent No.
US 9,989,592
App. No.
14/975,685
Granted
Jun 5, 2018
Kind
B2
Abstract

Existing multi-wire debugging protocols, such as 4-wire JTAG, 2-wire cJTAG, or ARM SWD, are run through a serial wireless link by providing the debugger and the target device with hardware interfaces that include UARTs and conversion bridges. The debugger interface serializes outgoing control signals and de-serializes returning data. The target interface de-serializes incoming control signals and serializes outgoing data. The actions of the interfaces are transparent to the inner workings of the devices, allowing re-use of existing debugging software. Compression, signal combining, and other optional enhancements increase debugging speed and flexibility while wirelessly accessing target devices that may be too small, too difficult to reach, or too seal-dependent for a wired connection.

Claims (20)

1. A debugger, comprising:

a wireless communication block;

a controller;

a conversion bridge coupled to the controller, the conversion bridge to:

convert a first multi-wire protocol signal received from the controller into a first serial signal for transmission by the wireless communication block; and

convert a second serial signal received by the wireless communication block to a second multi-wire protocol signal for analysis or storage by the controller; and

a de-multiplexer coupled to the wireless communication block, the conversion bridge, and the controller, the de-multiplexer to separate a combined serial signal from the wireless communication block into the second serial signal and a third serial signal, wherein the de-multiplexer is to provide the second serial signal to the conversion bridge, and wherein the de-multiplexer is to provide the third serial signal to the controller.

2. The debugger of claim 1 , wherein the analysis comprises a comparison of the second multi-wire protocol signal with a set of expected values.

3. The debugger of claim 1 , further comprising compression circuitry coupled to the wireless communication block, wherein the compression circuitry is to:

compress the first serial signal prior to transmission of the first serial signal by the wireless communication block; and

decompress the combined serial signal prior to separation by the de-multiplexer.

4. A system, comprising:

a first wireless communication block to be coupled to a first device; and

a second wireless communication block to be coupled to a second device, wherein a wireless link is to be established between the first wireless communication block and the second wireless communication block, wherein the first wireless communication block is to transmit a control signal to the second wireless communication block via the wireless link, wherein the second wireless communication block is to transmit a trace signal to the first wireless communication block via the wireless link in response to the control signal, wherein the first wireless communication block and the second wireless communication block are to remain activated until the later of an end-of-communication signal from the first wireless communication block or an end of a last trace signal, and wherein the second device is to begin receiving and reacting to the control signal after being supplied with power and before completing a boot cycle.

5. The system of claim 4 , further comprising an applications processor coupled to the second wireless communication block, wherein the second wireless communication block or the applications processor comprises a Universal Asynchronous Receiver/Transmitter (UART).

6. The system of claim 4 , wherein the wireless link comprises Bluetooth technology.

7. The system of claim 4 , wherein the wireless link comprises wireless fidelity (WiFi), wireless gigabit (WiGig), cellular phone, or near-field communication (NFC) technology.

8. The system of claim 4 , wherein the wireless link comprises a peer-to-peer link.

9. The system of claim 4 , wherein the first device and the second device are to be connected to a common network.

10. The system of claim 4 , wherein the first device and the second device are to be paired for establishment of the wireless link.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 2, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 057060/0431 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 9, 2021
From: INTEL IP CORPORATION
To: INTEL CORPORATION
Reel/Frame 057254/0415 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2017
From: MENON, SANKARAN; SMITH, BRADLEY; HUANG, JINSHI; KUEHNIS, ROLF
To: INTEL IP CORPORATION
Reel/Frame 040833/0483 →