Delay circuit, oscillation circuit, and semiconductor device
View Patent ↗Provided is a voltage regulator which consumes low power and uses an NMOS transistor as an output transistor. A delay circuit includes, between a constant current circuit and a capacitor, a depletion type NMOS transistor having a gate and a back gate each connected to a ground terminal, the constant current circuit including a depletion type NMOS transistor and a resistor connected between each of a gate and a back gate of the depletion type NMOS transistor and a source thereof.
1. A delay circuit, comprising:
a first NMOS transistor including a source connected to a ground terminal, and a gate to which an input signal is input;
a capacitor connected between a drain of the first NMOS transistor and the ground terminal;
a constant current circuit configured to cause a current to flow through the capacitor;
a first inverter including an input connected to an output terminal of the constant current circuit;
a second inverter including an input connected to an output terminal of the first inverter;
a first depletion type NMOS transistor including a gate and a back gate each connected to the ground terminal, and a source connected to the drain of the first NMOS transistor;
a second NMOS transistor including a source connected to the ground terminal, a drain connected to the output terminal of the constant current circuit, and a gate to which the input signal is input;
a third NMOS transistor including a gate connected to the output terminal of the first inverter, a source and a back gate each connected to a drain of the first depletion type NMOS transistor, and a drain connected to the output terminal of the constant current circuit; and
a fourth NMOS transistor including a source connected to the ground terminal, a gate connected to an output terminal of the second inverter, and a drain connected to the drain of the first NMOS transistor,
the constant current circuit comprising:
a second depletion type NMOS transistor; and
a resistor connected between each of a gate and a back gate of the second depletion type NMOS transistor and a source of the second depletion type NMOS transistor.
2. A semiconductor device, comprising:
the delay circuit of claim 1 ; and
a circuit to be controlled by a signal output from the delay circuit.
3. A delay circuit, comprising:
an input terminal;
a first output terminal;
a second output terminal;
a constant current circuit including an input terminal connected to a power supply terminal, and an output terminal connected to the first output terminal;
a first depletion type NMOS transistor including a gate and a back gate each connected to a ground terminal, and a drain connected to the output terminal of the constant current circuit;
a capacitor connected between the ground terminal and each of a source of the first depletion type NMOS transistor and the second output terminal;
a first NMOS transistor including a gate connected to the input terminal, and a drain connected to the output terminal of the constant current circuit; and
a second NMOS transistor including a gate connected to the input terminal, a drain connected to a source of the first NMOS transistor, and a source connected to the ground terminal,
the constant current circuit comprising:
a second depletion type NMOS transistor; and
a resistor connected between each of a gate and a back gate of the second depletion type NMOS transistor and a source of the second depletion type NMOS transistor.
4. An oscillator circuit, comprising:
the delay circuit of claim 3 ; and
a logic circuit configured to output a signal for controlling the delay circuit, to the input terminal of the delay circuit in response to output signals output from the first output terminal and the second output terminal of the delay circuit.
5. A semiconductor device, comprising the oscillator circuit of claim 4 .