Level shifter

1. A level shifter comprising:

a first and a second transistor coupled to a first power supply voltage terminal supplied with a second power supply voltage in parallel, the first transistor including a first gate connected to a drain of the second transistor and a first gate insulating film, and the second transistor including a second gate connected to a drain of the first transistor and a second gate insulating film;

a third and a fourth transistor coupled to a reference voltage terminal in parallel, the third transistor including a third gate supplied with a first control signal and a third gate insulating film, and the fourth transistor including a fourth gate supplied with a second control signal and a fourth gate insulating film;

a first and a second depression transistor, the first depression transistor being coupled between the first and the third transistor and including a fifth gate supplied with a third control signal and a fifth gate insulating film, the second depression transistor being coupled between the second and the fourth transistor and including a sixth gate supplied with a fourth control signal and a sixth gate insulating film; and

a timing control unit placed between a second power supply voltage terminal supplied with a second power supply voltage lower than the first power supply voltage and the reference voltage terminal, that generates the first control signal and the third control signal different from the first control signal corresponding to an inverted signal of an input signal, and generates the second control signal and the fourth control signal different from the second control signal corresponding to a non-inverted signal of the input signal,

wherein the third and the fourth gate insulating film is thinner than the first, the second, the fifth and the sixth gate insulating film.

2. The level shifter according to claim 1 , wherein the timing control unit generates the third and the fourth control signal with a lower slew rate at a rising edge than those of the first and the second control signal, and generates the first and second control signals with a lower slew rate at a falling edge than those of the third and the fourth control signal.

3. The level shifter according to claim 1 , wherein

the timing control unit comprises:

a first timing control circuit that generates the first and the third control signal, and

a second timing control circuit that generates the second and the fourth control signal,

wherein the first timing control circuit includes:

a fifth and a sixth transistor coupled in series between the second power supply voltage terminal and the reference voltage terminal and each including a gate supplied with the input signal, and

a first resistor placed between the fifth and the sixth transistor,

wherein the second timing control circuit includes:

a seventh and an eighth transistor coupled in series between the second power supply voltage terminal and the reference voltage terminal and each including a gate supplied with an inverted signal of the input signal, and

a second resistor placed between the seventh and the eighth transistor,

wherein the first timing control circuit supplies a voltage at a node between the fifth transistor and the first resistor to the third transistor as the first control signal, and supplies a voltage at a node between the sixth transistor and the first resistor to the first depression transistor as the third control signal, and

wherein the second timing control circuit supplies a voltage at a node between the seventh transistor and the second resistor to the fourth transistor as the second control signal, and supplies a voltage at a node between the ninth transistor and the second resistor to the second depression transistor as the fourth control signal.

4. The level shifter according to claim 3 , wherein each of the first and second resistors comprises a transfer gate.

5. The level shifter according to claim 1 , wherein

the timing control unit comprises a first and a second timing control circuit,

wherein the first timing control circuit includes:

a fifth and a sixth transistor coupled in series between the second power supply voltage terminal and the reference voltage terminal, and each including a gate supplied with the input signal, and

a seventh and an eighth transistor coupled in series between the second power supply voltage terminal and the reference voltage terminal and each including a gate supplied with the input signal,

wherein the second timing control circuit includes:

a ninth and a tenth transistor coupled in series between the second power supply voltage terminal and the reference voltage terminal and each including a gate supplied with the inverted signal of the input signal, and

an eleventh and a twelfth transistor coupled in series between the second power supply voltage terminal and the reference voltage terminal and each including a gate supplied with the inverted signal of the input signal,

wherein the first timing control circuit supplies a voltage at a node between the fifth and the sixth transistor to the third transistor as the first control signal, and supplies a voltage at a node between the seventh and the eighth transistors to the first depression transistor as the third control signal, and

the second timing control circuit supplies a voltage at a node between the ninth and the tenth transistor the fourth transistor as the second control signal, and supplies a voltage at a node between the eleventh and the twelfth transistor to the second depression transistor as the fourth control signal.

6. The level shifter according to claim 5 , wherein the fifth, the seventh, the ninth and the eleventh transistor comprises a PMOS transistor, the sixth, the eighth, the tenth and the twelfth transistor comprises an NMOS transistor,

wherein a driving capability of the fifth transistor is higher than a driving capability of the seventh transistor,

wherein a driving capability of the sixth transistor is lower than a driving capability of the eighth transistor,

wherein a driving capability of the ninth transistor is higher than a driving capability of the eleventh transistor, and

wherein a driving capability of the tenth transistor is lower than a driving capability of the twelfth transistor.

7. The level shifter according to claim 1 , wherein

the timing control unit comprises:

a fifth and a sixth transistor coupled in series between the second power supply voltage terminal and the reference voltage terminal and each including a gate supplied with the input signal, and a gate insulating film thinner than the first, the second, the fifth and the sixth gate insulating film,

a first resistor placed between the fifth and the sixth transistor,

wherein the timing control circuit supplies a voltage at a node between the fifth transistor and the first resistor to the third transistor as the first control signal, supplies a voltage at a node between the sixth transistor and the first resistor to the first depression transistor as the third control signal, supplies an inverted signal of the first control signal to the second depression transistor as the fourth control signal, and supplies an inverted signal of the third control signal to the fourth transistor as the second control signal.

8. The level shifter according to claim 1 , wherein

the timing control unit comprises:

a fifth and a sixth transistor coupled in series between the second power supply voltage terminal and the reference voltage terminal, and each including a gate supplied with the input signal, and

a seventh and an eighth transistor coupled in series between the second power supply voltage terminal and the reference voltage terminal and each including a gate supplied with the input signal,

wherein the timing control circuit supplies a voltage at a node between the fifth and the sixth transistor to the third transistor as the first control signal, and supplies a voltage at a node between the seventh and the eighth transistors to the first depression transistor as the third control signal, and

wherein the timing control circuit supplies a voltage at a node between the fifth and the sixth transistor to the third transistor as the first control signal, supplies a voltage at a node between the seventh and the eighth transistor to the first depression transistor as the third control signal, supplies an inverted signal of the first control signal to the second depression transistor as the fourth control signal, and supplies an inverted signal of the third control signal to the fourth transistor as the second control signal.

9. The level shifter according to claim 8 , wherein the fifth, the seventh transistor comprises a PMOS transistor, the sixth, the eighth transistor comprises an NMOS transistor,

wherein a driving capability of the fifth transistor is higher than a driving capability of the seventh transistor, and

wherein a driving capability of the sixth transistor is lower than a driving capability of the eighth transistor.