RF impedance matching network
A control circuit for a impedance matching circuit having first and second capacitor arrays receives as input one or more RF parameters of the impedance matching circuit, and in response thereto: determines a first match configuration for the first capacitor array and a second match configuration for the second capacitor array to create an impedance match between a fixed RF source impedance and a variable RF load impedance, the first match configuration and the second match configuration being determined from one or more look-up tables and based upon the detected one or more RF parameters; and alters at least one of the first array configuration and the second array configuration to the first match configuration and the second match configuration, respectively, by controlling the on and off states of (a) each discrete capacitor of the first capacitor array and (b) each discrete capacitor of the second capacitor array.
1. An RF impedance matching network comprising:
an RF input configured to be operatively coupled to an RF source, the RF source having a single fixed RF source impedance;
an RF output configured to be operatively coupled to an RF load, the RF load comprising a plasma chamber and having a variable RF load impedance;
an impedance matching circuit operatively coupled between the RF source and the RF output, the impedance matching circuit comprising:
a first capacitor array comprising a first plurality of discrete capacitors and having a first array configuration which defines on and off states of the first plurality of discrete capacitors; and
a second capacitor array comprising a second plurality of discrete capacitors and having a second array configuration which defines on and off states of the second plurality of discrete capacitors;
an RF sensor operatively coupled to the RF input, the RF sensor configured to detect one or more RF parameters of the impedance matching circuit; and
a control circuit operatively coupled to the first capacitor array and the second capacitor array, wherein the control circuit is configured to:
determine an initial input impedance at the RF input of the impedance matching circuit when there is not an impedance match between the single fixed RF source impedance and the variable RF load impedance, the input impedance based on the detected one or more RF parameters;
determine the variable RF load impedance from a parameter matrix look-up table using the determined input impedance, the first array configuration, and the second array configuration;
after determining the variable RF load impedance, determine a first match configuration for the first capacitor array and a second match configuration for the second capacitor array to create the impedance match between the single fixed RF source impedance and the variable RF load impedance, the first match configuration and the second match configuration being determined from an array configuration look-up table using the determined variable RF load impedance; and
alter at least one of the first array configuration and the second array configuration to the first match configuration and the second match configuration, respectively, by controlling the on and off states of (a) each discrete capacitor of the first plurality of discrete capacitors and (b) each discrete capacitor of the second plurality of discrete capacitors.
2. The RF impedance matching network of claim 1 , wherein the parameter matrix look-up table comprises a plurality of S-parameter matrices.
3. The RF impedance matching network of claim 2 , wherein the parameter matrix look-up table comprises, for each S-parameter matrix, a conversion to a Z-parameter matrix.
4. The RF impedance matching network of claim 1 , wherein the parameter matrix look-up table comprises, for each combination of potential first array configurations and potential second array configurations, a parameter matrix indicative of the load impedance.
5. The RF impedance matching network of claim 1 , wherein the parameter matrix look-up table comprises a plurality of Z-parameter matrices.
6. The RF impedance matching network of claim 1 , wherein the RF sensor is operatively coupled to the RF input, and the detected one or more RF parameters include a voltage parameter and a current parameter.
7. A method of manufacturing a semiconductor, the method comprising:
placing a substrate in a plasma chamber configured to deposit a material layer onto the substrate or etch a material layer from the substrate; and
coupling an impedance matching circuit between an RF source and the plasma chamber, the impedance matching circuit comprising:
an RF input configured to be operatively coupled to the RF source, the RF source having a single fixed RF source impedance;
an RF output configured to be operatively coupled to the plasma chamber, the plasma chamber having a variable plasma chamber impedance;
a first capacitor array comprising a first plurality of discrete capacitors and having a first array configuration which defines on and off states of the first plurality of discrete capacitors; and
a second capacitor array comprising a second plurality of discrete capacitors and having a second array configuration which defines on and off states of the second plurality of discrete capacitors; and
energizing plasma within the plasma chamber by coupling RF power from the RF source into the plasma chamber to perform a deposition or etching, and while energizing the plasma:
detecting one or more RF parameters of the impedance matching circuit at the RF input of the impedance matching circuit;
determining an initial input impedance at the RF input of the impedance matching circuit when there is not an impedance match between the single fixed RF source impedance and the variable RF load impedance, the input impedance based on the detected one or more RF parameters;
determining the variable plasma chamber impedance from a parameter matrix look-up table using the determined input impedance, the first array configuration, and the second array configuration;
after determining the variable plasma chamber impedance, determining a first match configuration for the first capacitor array and a second match configuration for the second capacitor array to create the impedance match between the single fixed RF source impedance and the variable plasma chamber impedance, the first match configuration and the second match configuration being determined from an array configuration look-up table using the determined variable plasma chamber impedance; and
altering at least one of the first array configuration and the second array configuration to the first match configuration and the second match configuration, respectively, by controlling the on and off states of (a) each discrete capacitor of the first plurality of discrete capacitors and (b) each discrete capacitor of the second plurality of discrete capacitors.
8. The method of claim 7 , wherein the parameter matrix look-up table comprises a plurality of S-parameter matrices.
9. The method of claim 8 , wherein the parameter matrix look-up table comprises, for each S-parameter matrix, a conversion to a Z-parameter matrix.
10. The method of claim 7 , wherein the parameter matrix look-up table comprises, for each combination of potential first array configurations and potential second array configurations, a parameter matrix indicative of the plasma chamber impedance.
11. The method of claim 7 , wherein the parameter matrix look-up table comprises a plurality of Z-parameter matrices.
12. A method of impedance matching comprising:
coupling an impedance matching circuit between an RF source and an RF load, the RF source having a single fixed RF source impedance, the RF load comprising a plasma chamber and having a variable RF load impedance, and the impedance matching circuit comprising:
an RF input configured to be operatively coupled to the RF source;
an RF output configured to be operatively coupled to the RF load;
a first capacitor array comprising a first plurality of discrete capacitors and having a first array configuration which defines on and off states of the first plurality of discrete capacitors; and
a second capacitor array comprising a second plurality of discrete capacitors and having a second array configuration which defines on and off states of the second plurality of discrete capacitors;
detecting one or more RF parameters of the impedance matching circuit at the RF input of the impedance matching circuit;
determining an initial input impedance at the RF input of the impedance matching circuit when there is not an impedance match between the single fixed RF source impedance and the variable RF load impedance, the input impedance based on the detected one or more RF parameters;
determining the variable RF load impedance from a parameter matrix look-up table using the determined input impedance, the first array configuration, and the second array configuration;
after determining the variable RF load impedance, determining a first match configuration for the first capacitor array and a second match configuration for the second capacitor array to create the impedance match between the single fixed RF source impedance and the variable RF load impedance, the first match configuration and the second match configuration being determined from an array configuration look-up table using the determined variable RF load impedance; and
altering at least one of the first array configuration and the second array configuration to the first match configuration and the second match configuration, respectively, by controlling the on and off states of (a) each discrete capacitor of the first plurality of discrete capacitors and (b) each discrete capacitor of the second plurality of discrete capacitors.
13. The method of claim 12 , wherein the parameter matrix look-up table comprises, for each combination of potential first array configurations and potential second array configurations, a parameter matrix indicative of the load impedance.
14. A semiconductor processing tool comprising:
a plasma chamber configured to deposit a material onto a substrate or etch a material from the substrate; and
an impedance matching circuit operably coupled to the plasma chamber, matching circuit comprising:
an RF input configured to be operably coupled to an RF source, the RF source having a single fixed RF source impedance;
an RF output operably coupled to the plasma chamber, the plasma chamber having a variable RF load impedance;
a first capacitor array comprising a first plurality of discrete capacitors and having a first array configuration which defines on and off states of the first plurality of discrete capacitors; and
a second capacitor array comprising a second plurality of discrete capacitors and having a second array configuration which defines on and off states of the second plurality of discrete capacitors;
an RF sensor operably coupled to the RF input, the RF sensor configured to detect one or more RF parameters of the impedance matching circuit; and
a control circuit operably coupled to the first capacitor array and the second capacitor array, wherein the control circuit is configured to:
determine an initial input impedance at the RF input of the impedance matching circuit when there is not an impedance match between the single fixed RF source impedance and the variable RF load impedance, the input impedance based on the detected one or more RF parameters;
determine the variable RF load impedance from a parameter matrix look-up table using the determined input impedance, the first array configuration, and the second array configuration;
after determining the variable RF load impedance, determine a first match configuration for the first capacitor array and a second match configuration for the second capacitor array to create the impedance match between the single fixed RF source impedance and the variable RF load impedance, the first match configuration and the second match configuration being determined from an array configuration look-up table using the determined variable RF load impedance; and
alter at least one of the first array configuration and the second array configuration to the first match configuration and the second match configuration, respectively, by controlling the on and off states of (a) each discrete capacitor of the first plurality of discrete capacitors and (b) each discrete capacitor of the second plurality of discrete capacitors.