Trench IGBT with waved floating P-well electron injection
View Patent ↗A trench IGBT includes a floating P well and a floating N+ well that extends down into the floating P well. A bottom surface of the floating P well has a novel waved contour so that it has thinner portions and thicker portions. When the IGBT is on, electrons flow from an N+ emitter, vertically through a channel along a trench sidewall, and to an N− type drift layer. Additional electrons flow through the channel but then pass under the trench, through the floating P well to the floating N+ well, and laterally through the floating N+ well. NPN transistors are located at thinner portions of the floating P type well. The NPN transistors inject electrons from the floating N+ type well down into the N− drift layer. The extra electron injection reduces V CE(SAT) . The waved contour can be made without adding any masking step to an IGBT manufacturing process.
1. An Insulated Gate Bipolar Transistor (IGBT) die structure comprising:
a P type collector layer;
an N− type drift layer disposed over the P type collector layer;
a P type body region that extends into the N− type drift layer;
an N+ type emitter region, wherein the N+ type emitter region extends into the P type body region from a substantially planar upper semiconductor surface;
a floating P type well region that extends into the N− type drift layer and that is laterally separated from the P type body region, and wherein the floating P type well region has at least one thinner portion disposed between two of a plurality of thicker portions;
a floating N+ type well region that extends into the floating P type well region from the substantially planar upper semiconductor surface, wherein the floating P type well region is separated from the substantially planar upper semiconductor surface by the floating N+ type well region, and wherein the floating N+ type well region extends over the at least one thinner portion;
a trench gate electrode disposed in a trench, wherein the trench gate electrode is disposed at least in part between the P type body region on one side of the trench and the floating P type well region and the floating N+ type well region on an opposite side of the trench;
a first metal terminal, wherein the first metal terminal is coupled to the P type body region and to the N+ type emitter region;
a second metal terminal, wherein the second metal terminal is coupled to the trench gate electrode; and
a third metal terminal that is coupled to the P type collector layer.
2. The IGBT die structure of claim 1 , further comprising:
an N+ type buffer layer disposed between the P type collector layer and the N− type drift layer.
3. The IGBT die structure of claim 1 , wherein the at least one thinner portion of the floating P type well region is less than half as thick as each of the thicker portions of the floating P type well region.
4. The IGBT die structure of claim 1 , wherein the trench extends from the substantially planar upper semiconductor surface to a depth DT, wherein the P type body region extends to a depth DP 1 measured from the substantially planar upper semiconductor surface, wherein the thicker portions of the floating P type well region extend to a depth DP 2 THICK measured from the substantially planar upper semiconductor surface, wherein DT is greater than DP 1 , and wherein DT is greater than DP 2 THICK.
5. The IGBT die structure of claim 4 , wherein the floating P type well region forms a part of a sidewall of the trench, wherein the floating P type well region at the sidewall at a location immediately adjacent the trench extends to the depth DP 2 THICK.
6. The IGBT die structure of claim 4 , wherein the floating N+ type well region has a polygonal outer periphery when the trench IGBT die structure is considered from a top-down perspective, wherein the floating P type well region has the same polygonal outer periphery when the trench IGBT die structure is considered from the top-down perspective, and wherein the trench extends around the outer periphery of the floating N+ type well region and the floating P type well region such that it surrounds the floating N+ type well region and the floating P type well region when the trench IGBT die structure is considered from the top-down perspective.
7. The IGBT die structure of claim 6 , wherein the floating P type well region at all locations along its polygonal outer periphery extends to the depth DP 2 THICK.
8. The IGBT die structure of claim 6 , wherein the polygonal outer periphery of the floating P type well region has a shape taken from the group consisting of: an octagon, a square with rounded corners, a rectangle, a rectangle with rounded corners, a rectangular strip.
9. The IGBT die structure of claim 6 , wherein the N+ type emitter region forms a sidewall of the trench, and wherein the N+ type emitter region does not entirely loop around the polygonal outer periphery of the floating N+ type well region and the floating P type well region when the trench IGBT die structure is considered from the top-down perspective.
10. The IGBT die structure of claim 6 , wherein the N+ type emitter region is a first N+ type emitter region, wherein the IGBT die structure further comprises a second N+ type emitter region, a third N+ type emitter region, and a fourth N+ type emitter region, wherein the first N+ type emitter region extends along a first planar sidewall of the trench, wherein the second N+ type emitter region extends along a second planar sidewall of the trench, wherein the third N+ type emitter region extends along a third planar sidewall of the trench, and wherein the fourth N+ type emitter region extends along a fourth planar sidewall of the trench.
11. The IGBT die structure of claim 1 , wherein a first thinner portion of the floating P type well region has a substantially polygonal shape when the IGBT die structure is considered from a top-down perspective.
12. The IGBT die structure of claim 11 , wherein a second thinner portion of the floating P type well region has a substantially polygonal shape when the IGBT die structure is considered from the top-down perspective, wherein the second thinner portion loops around the first thinner portion such that the first and second thinner portions are concentric polygons when considered from the top-down perspective of the IGBT die structure.
13. An Insulated Gate Bipolar Transistor (IGBT) die structure comprising:
a P type collector layer;
an N− type drift layer disposed over the P type collector layer;
a P type body region that extends into the N− type drift layer;
an N+ type emitter region, wherein the N+ type emitter region extends into the P type body region from a substantially planar upper semiconductor surface;
a floating P type well region that extends into the N− type drift layer and that is laterally separated from the P type body region, wherein the floating P type well region has a thinner portion disposed between two of a plurality of thicker portions, wherein the thinner portion of the floating P type well region is less than half as thick as the thicker portions of the floating P type well region, wherein the thinner portion of the floating P type well region extends to a depth DP 2 THIN measured from the substantially planar upper semiconductor surface, wherein the floating P type well region has a polygonal outer periphery when the trench IGBT die structure is considered from a top-down perspective, and wherein the floating P type well region at all locations along its polygonal outer periphery extends to a depth greater than DP 2 THIN measured from the substantially planar upper semiconductor surface;
a trench gate electrode disposed in a trench, wherein the trench gate electrode is disposed at least in part between the P type body region on one side of the trench and the floating P type well region on an opposite side of the trench;
a first metal terminal, wherein the first metal terminal is coupled to the P type body region and to the N+ type emitter region;
a second metal terminal, wherein the second metal terminal is coupled to the trench gate electrode; and
a third metal terminal that is coupled to the P type collector layer.
14. The IGBT die structure of claim 13 , wherein the thinner portion of the floating P type well has a polygonal shape when the trench IGBT die structure is considered from the top-down perspective.
15. The IGBT die structure of claim 14 , further comprising:
means for conducting electrons in an IGBT on state laterally in a plane that is parallel with a plane of the substantially planar upper semiconductor surface and for injecting at least some of the electrons vertically down into the N− type drift region, wherein the at least some electrons that are injected down into the N− type drift region are injected at locations none of which is disposed under the trench and none of which is disposed under the P type body region.
16. The IGBT die structure of claim 15 , wherein the means comprises a floating N+ type well region that extends a distance DN into the floating P type well region from the substantially planar upper semiconductor surface, wherein the floating N+ type well region extends over the at least one thinner portion.
17. The IGBT die structure of claim 16 , wherein the quantity DP 2 THIN minus DN is less than half the quantity DP 2 THICK minus DN.