IP Library Granted Patent US 10,043,735
Granted Patent B2
US 10,043,735 · App. 14/988,180 · Granted Aug 7, 2018

Semiconductor module, semiconductor device, and method for manufacturing semiconductor devices

Inventor: Hirotaka Ohno (Miyoshi, JP)
Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
H01L23/49562H01L23/40H01L23/4012H01L23/473H01L23/49575H01L25/117H01L25/50H01L23/49537
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Quick Facts
Patent No.
US 10,043,735
App. No.
14/988,180
Granted
Aug 7, 2018
Kind
B2
Abstract

A semiconductor module includes: first semiconductor devices; second semiconductor devices; a first and second wires. Each first semiconductor device comprises: first sealing resin; first-third terminals; a first semiconductor chip connected to the first and third terminals. Each second semiconductor device comprises: second sealing resin; fourth-sixth terminals; a second semiconductor chip connected to the fourth and fifth terminals, and not connected to the sixth terminal. The first and second semiconductor devices are stacked along a stacking direction. The first terminals and the fourth terminals are arranged in a line along the stacking direction. The second terminals and the fifth terminals are arranged in a line along the stacking direction. The third terminals and the sixth terminals are arranged in a line along the stacking direction. The first wire is connected to the fifth terminals. The second wire is connected to the third terminals.

Claims (47)

1. A semiconductor module, comprising:

a first wire;

a second wire;

a plurality of first semiconductor devices, each one of the first semiconductor devices comprising:

first sealing resin;

first, second, and third terminals, each of which projects from inside to outside of the first sealing resin; and

a first semiconductor chip located inside the first sealing resin and connected to at least the first and third terminals; and

a plurality of second semiconductor devices, each one of the second semiconductor devices comprising:

second sealing resin;

fourth, fifth, and sixth terminals, each of which projects from inside to outside of the second sealing resin; and

a second semiconductor chip located inside the second sealing resin, connected to the fourth and fifth terminals, and not connected to the sixth terminal,

wherein the first semiconductor devices and the second semiconductor devices are stacked along a stacking direction,

the first terminals and the fourth terminals are arranged in a line along the stacking direction,

the second terminals and the fifth terminals are arranged in a line along the stacking direction,

the third terminals and the sixth terminals are arranged in a line along the stacking direction,

the first wire extends along the line of the second terminals and the fifth terminals, and is connected to the fifth terminals, and

the second wire extends along the line of the third terminals and the sixth terminals, and is connected to the third terminals.

2. The semiconductor module of claim 1 , wherein a portion of the each sixth terminal that is located inside the second sealing resin comprises an anchor portion configured to be pressed to the second sealing resin when the sixth terminal is pulled from the inside toward the outside of the second sealing resin.

3. The semiconductor module of claim 1 , wherein the second wire is connected to the sixth terminals.

4. The semiconductor module of claim 1 , wherein the second wire is not connected to the sixth terminals.

5. A semiconductor device, comprising:

a semiconductor chip;

sealing resin sealing the semiconductor chip;

a first valid terminal projecting from inside to outside of the sealing resin and connected to the semiconductor chip inside the sealing resin;

a second valid terminal projecting from the inside to the outside of the sealing resin and connected to the semiconductor chip inside the sealing resin; and

a dummy terminal projecting from the inside to the outside of the sealing resin and not connected to the semiconductor chip inside the sealing resin,

wherein a portion of the dummy terminal located inside the sealing resin comprises an anchor portion configured to be pressed to the sealing resin when the dummy terminal is pulled from the inside toward the outside of the sealing resin.

6. A method for manufacturing a first semiconductor device and a second semiconductor device using a common mold, the method comprising:

manufacturing the first semiconductor device from a first semi-product; and

manufacturing the second semiconductor device from a second semi-product,

wherein the common mold comprises:

a cavity; and

first, second, and third receiving grooves, each of which is connected to the cavity,

the first semi-product comprises:

a first semiconductor chip;

first and third terminals, each of which is connected to the first semiconductor chip; and

a second terminal,

the second semi-product comprises:

a second semiconductor chip;

fourth and fifth terminals, each of which is connected to the second semiconductor chip; and

a sixth terminal spaced from the second semiconductor chip,

the manufacturing of the first semiconductor device comprises:

setting the first semi-product to the common mold so that the first semiconductor chip is located in the cavity, the first terminal is located in the first receiving groove, the second terminal is located in the second receiving groove, and the third terminal is located in the third receiving groove; and

sealing the first semiconductor chip with sealing resin using the common mold after the setting of the first semi-product, and

the manufacturing of the second semiconductor device comprises:

setting the second semi-product to the common mold so that the second semiconductor chip is located in the cavity, the fourth terminal is located in the first receiving groove, the fifth terminal is located in the second receiving groove, and the sixth terminal is located in the third receiving groove; and

sealing the second semiconductor chip with sealing resin using the common mold after the setting of the second semi-product.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: TOYOTA JIDOSHA KABUSHIKI KAISHA
To: DENSO CORPORATION
Reel/Frame 052285/0419 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 5, 2016
From: OHNO, HIROTAKA
To: TOYOTA JIDOSHA KABUSHIKI KAISHA
Reel/Frame 037411/0687 →
Priority Claims (1)
JP 2015-035491 · Feb 25, 2015 · national
Continuity (1)
Related Publication 20160247793A1 · Aug 25, 2016