Interposer with TAP, trigger, address/data bus, and analog monitor circuitry
The disclosure describes a novel method and apparatus for improving interposers to include embedded monitoring instruments for real time monitoring digital signals, analog signals, voltage signals and temperature sensors located in the interposer. An embedded monitor trigger unit controls the starting and stopping of the real time monitoring operations. The embedded monitoring instruments are accessible via an 1149.1 TAP interface on the interposer.
1. An interposer comprising:
(a) a test access port having a test data input lead, a test data output lead, a test clock lead, a test mode select lead, and test control leads;
(b) functional circuitry leads that include an address bus, a data bus, functional control signals, a voltage bus, a ground bus, and analog signals;
(c) monitor trigger circuitry having inputs coupled to the functional circuitry leads, the test data input lead, and the test control leads, and having an output coupled to the test data output lead, and monitor control outputs;
(d) address and data bus monitor circuitry having inputs coupled to the functional circuitry leads, to the monitor control outputs, an input coupled to the test data input lead, an input coupled to the test control leads, and an output coupled to the test data output lead; and
(e) voltage and analog signal monitor circuitry having inputs coupled to the functional circuitry leads, to the monitor control outputs, an input coupled to the test data input lead, an input coupled to the test control leads, and an output coupled to the test data output lead.
2. The interposer of claim 1 in which the test access port includes state machine circuitry having inputs coupled with the test clock lead and the test mode select lead, and having state outputs coupled with the test control leads.
3. The interposer of claim 1 including a silicon substrate having top and bottom surfaces and in which the functional circuitry leads include through silicon vias coupling leads on the top and bottom surfaces of the substrate.
4. The interposer of claim 1 including a silicon substrate having top and bottom surfaces and in which the test data input lead, the test data output lead, the test clock lead, and the test mode select lead include through silicon vias coupling leads on the top and bottom surfaces of the substrate.
5. The interposer of claim 1 including a silicon substrate having top and bottom surfaces and in which the functional circuitry leads include through silicon vias coupling leads on the top and bottom surfaces of the substrate and in which the test data input lead, the test data output lead, the test clock lead, and the test mode select lead include through silicon vias coupling leads on the top and bottom surfaces of the substrate.
6. The interposer of claim 1 in which the address and data bus monitor circuitry is free of any connection to the analog signals and the voltage and analog signal monitor circuitry is coupled to the voltage bus, the ground bus, and the analog signals.