IP Library Granted Patent US 10,193,324
Granted Patent B2
US 10,193,324 · App. 14/991,259 · Granted Jan 29, 2019

Low-loss and fast acting solid-state breaker

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Quick Facts
Patent No.
US 10,193,324
App. No.
14/991,259
Granted
Jan 29, 2019
Kind
B2
Abstract

A circuit including a source, a load, and an isolation circuit for controllably isolating the load from the source. The isolation circuit is disposed between the source and the load. The isolation circuit includes at least one insulated-gate bipolar transistor (IGBT) and at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor. When no fault condition exists, the GTO is configured to be on to couple the load to the source. When a fault condition exists, the at least one IGBT is configured to turn on. After the at least one IGBT turns on, the at least one GTO is configured to turn off. After a predetermined amount of time after the at least one GTO turns off, the at least one IGBT is configured to turn off.

Claims (60)

1. A circuit for isolating a load from a source, the circuit comprising:

at least one insulated-gate bipolar transistor (IGBT); and

at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor,

wherein when no fault condition exists, the at least one GTO is configured to be on to couple the load to the source, and

wherein when a fault condition exists:

the at least one IGBT is configured to turn on; and

the at least one GTO is configured to turn off after the at least one IGBT turns on.

2. The circuit of claim 1 , wherein

the at least one IGBT comprises a collector, a gate, and an emitter, and

the at least one GTO comprises an anode, a gate, and a cathode,

wherein the collector of the at least one IGBT is connected to the anode of the at least one GTO, and

wherein the emitter of the at least one IGBT is connected to the cathode of the at least one GTO.

3. The circuit of claim 1 , wherein the at least one GTO is a super GTO.

4. The circuit of claim 1 ,

wherein when the fault condition exists,

the at least one IGBT is configured to turn off a predetermined amount of time after the at least one GTO turns off.

5. A circuit comprising:

a source;

a load; and

an isolation circuit disposed between the source and the load, the isolation circuit comprising:

at least one insulated-gate bipolar transistor (IGBT); and

at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor,

wherein when no fault condition exists the at least one GTO is configured to be on to couple the load to the source, and

wherein when a fault condition exists:

the at least one IGBT is configured to turn on; and

the at least one GTO is configured to turn off after the at least one IGBT turns on.

6. The circuit of claim 5 ,

wherein when the fault condition exists,

the at least one IGBT is configured to turn off a predetermined amount of time after the at least one GTO turns off.

7. The circuit of claim 6 , wherein the predetermined amount of time is based on the operating temperature of the at least one GTO.

8. The circuit of claim 7 , wherein the predetermined amount of time is further based on a rate of change of an expected fault current through the at least one IGBT.

9. The circuit of claim 6 , wherein the predetermined amount of time is based on a rate of change of an expected fault current through the at least one IGBT.

10. The circuit of claim 5 , further comprising a controller configured to detect when a fault condition exists and, when a fault conditions exists, to:

turn on the at least one IGBT;

turn off the at least one GTO after turning on the IGBT; and

turn off the at least one IGBT a predetermined amount of time after turning off the at least one GTO.

11. The circuit of claim 5 , wherein

the at least one IGBT comprises a collector, a gate, and an emitter, and

the at least one GTO comprises an anode, a gate, and a cathode,

wherein the collector of the at least one IGBT is connected to the anode of the at least one GTO, and

wherein the emitter of the at least one IGBT is connected to the cathode of the at least one GTO.

12. The circuit of claim 11 , further comprising a controller connected to the gate of the at least one IGBT and to the gate of the at least one GTO.

13. A circuit comprising:

a source;

a load; and

an isolation circuit disposed between the source and the load, the isolation circuit comprising:

at least one insulated-gate bipolar transistor (IGBT); and

at least one gate turn-off thyristor (GTO) in parallel with the insulated-gate bipolar transistor, wherein:

the at least one IGBT comprises a collector, a gate, and an emitter, and

the at least one GTO comprises an anode, a gate, and a cathode,

wherein:

the collector of the at least one IGBT is connected to the anode of the at least one GTO,

the emitter of the at least one IGBT is connected to the cathode of the at least one GTO, and

a controller connected to the gate of the at least one IGBT and to the gate of the at least one GTO is configured when no fault condition exists to supply a signal to the gate of the at least one GTO and when a fault conditions exists to:

supply a signal to the gate of the at least one IGBT to turn on the at least one IGBT; and

remove the signal from the gate of the at least one GTO to turn off the at least one GTO after turning on the IGBT.

14. The circuit of claim 13 , wherein after removing the signal from the gate of the at least one GTO, the circuit is further configured to remove the signal from the gate of the at least one IGBT to turn off the at least one IGBT a predetermined amount of time after turning off the at least one GTO, wherein the predetermined amount of time is based on the operating temperature of the at least one GTO.

15. The circuit of claim 14 , wherein the predetermined amount of time is further based on a rate of change of an expected fault current through the at least one IGBT.

16. The circuit of claim 13 , wherein after removing the signal from the gate of the at least one GTO, the circuit is further configured to remove the signal from the gate of the at least one IGBT to turn off the at least one IGBT a predetermined amount of time after turning off the at least one GTO, wherein the predetermined amount of time is based on a rate of change of an expected fault current through the at least one IGBT.

17. The circuit of claim 5 , further comprising a reactance in series with the isolation circuit.

Assignments (3)
SECURITY INTEREST Recorded Aug 12, 2022
From: EXCELITAS TECHNOLOGIES CORP.
To: GOLUB CAPITAL MARKETS LLC, AS COLLATERAL AGENT
Reel/Frame 061164/0582 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2020
From: SILICON POWER CORPORATION
To: EXCELITAS TECHNOLOGIES CORP.
Reel/Frame 054239/0230 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 29, 2016
From: WALDRON, JOHN E.; BRANDMIER, KENNETH; AZOTEA, JAMES K.
To: SILICON POWER CORPORATION
Reel/Frame 038126/0527 →