Power amplifier

1. A power amplifier comprising:

an amplifying circuit comprising

a first field effect transistor configured to amplify an input signal, and

a second field effect transistor connected to the first field effect transistor in a cascode structure, and configured to receive the signal amplified by the first field effect transistor and to output the received signal;

a feedback circuit connected to the amplifying circuit, and configured to feedback the signal amplified in the amplifying circuit into the amplifying circuit; and

a feedback controlling circuit connected to the feedback circuit, and configured to control a power of the signal fed-back by the feedback circuit based on a power of the input signal,

wherein the feedback controlling circuit is configured to control the feedback circuit to increase the power of the signal fed-back by the feedback circuit, in response to the power of the input signal input to the amplifying circuit being increased.

2. The power amplifier of claim 1 , wherein

the first field effect transistor is configured to amplify the input signal input through a gate terminal of the first field effect transistor and to output the amplified signal through a drain terminal of the first field effect transistor, and

the second field effect transistor is configured to receive the signal amplified by the first field effect transistor through a source terminal of the second field effect transistor and to output the received signal through a drain terminal of the second field effect transistor.

3. The power amplifier of claim 2 , wherein the feedback circuit comprises a feedback field effect transistor configured to pass the fed-back signal between a source terminal and a drain terminal of the feedback field effect transistor and to determine a power of the fed-back signal based on a voltage of a gate terminal of the feedback field effect transistor, and connected to the drain terminal of the second field effect transistor and the gate terminal of the first field effect transistor to feedback a signal amplified in the second field effect transistor into the first field effect transistor.

4. The power amplifier of claim 2 , wherein the feedback controlling circuit is connected to the gate terminal of the first field effect transistor to sense the power of the input signal, and provides a feedback voltage to the feedback circuit to control the power of the signal fed-back by the feedback circuit.

5. The power amplifier of claim 1 , wherein the feedback controlling circuit comprises:

a third field effect transistor configured to receive the input signal through a gate terminal of the third field effect transistor;

a fourth field effect transistor having a gate terminal connected to a drain terminal of the third field effect transistor;

a first capacitor connected to the drain terminal of the third field effect transistor and a source terminal of the fourth field effect transistor; and

a second capacitor connected to a source terminal of the third field effect transistor and the gate terminal of the fourth field effect transistor.

6. The power amplifier of claim 1 , wherein the amplifying circuit, the feedback circuit, and the feedback controlling circuit are formed using a complementary metal oxide semiconductor (CMOS) process.

7. The power amplifier of claim 1 , further comprising:

a first balun connected to the amplifying circuit, configured to convert the input signal from a single signal into differential signals; and

a second balun connected to the amplifying circuit, configured to convert the differential signals amplified by the amplifying circuit into a single signal.

8. The power amplifier of claim 1 , further comprising:

a first matching network connected to the amplifying circuit such that an input impedance of the amplifying circuit becomes a preset value; and

a second matching network connected to the amplifying circuit such that an output impedance of the amplifying circuit becomes a preset value.