Backside processed semiconductor device

1. A method of forming a semiconductor device, the method comprising:

providing a first substrate;

from a first surface of the first substrate, forming a shallow trench isolation in the first substrate, the shallow trench isolation having a pad layer at a first depth, the first depth being a distance from a bottom of the shallow trench isolation to the first surface of the first substrate;

forming at least one transistor on the first surface of the first substrate, the at least one transistor having a source/drain region at a seven depth, the seventh depth being a distance from the bottom of the source/drain region to the first surface of the first substrate;

forming a first dielectric cap layer covering the first surface of the first substrate;

forming a first interconnect structure on the first dielectric cap layer;

providing a carrier substrate;

bonding the carrier substrate to the first substrate through the first dielectric cap layer;

from a second surface of the first substrate opposite to the first surface, thinning the first substrate to the first depth to expose a surface of the pad layer;

after thinning the first substrate from the second surface, removing a portion of the first substrate from the second surface below the at least one transistor to a fifth depth lower than the first depth using a wet etching process, the fifth depth being a distance from the second surface to the first surface of the first substrate after removing the portion of the first substrate from the second surface below the at least one transistor, the fifth depth being greater than the seventh depth;

forming a second dielectric cap layer on the second surface of the first substrate covering the exposed surface of the pad layer of the shallow trench isolation and the portion of the first substrate below the at least one transistor having the fifth depth below the first depth;

forming a through silicon via (TSV), the TSV running through the second dielectric cap layer, the shallow trench isolation, and the first dielectric cap layer, and connected to the first interconnect structure; and

forming a second interconnect structure on the second dielectric cap layer connected to the through silicon via.

2. The method of claim 1 , wherein thinning the first substrate from the second surface of the first substrate comprises grinding the second surface to a sixth depth, performing a wet etching on the grounded surface to a second depth, the second depth being a distance from the second surface to the first surface of the first substrate after the wet etching, and performing a chemical mechanical polishing on the etched surface using the pad layer as a stop layer, the first substrate comprises a doped epitaxial layer having a third depth, the third depth being a distance from a bottom of the doped epitaxial layer to the first surface of the first substrate, the third depth being greater than or equal to the first depth.

3. The method of claim 1 , further comprising, before forming the shallow trench isolation, performing ion implantation from the first surface of the first substrate to form a first injection doped layer having a fourth depth, the fourth depth being a distance from a bottom of the first injection doped layer to the first surface of the first substrate, the fourth depth being greater than or equal to the first depth.

4. The method of claim 1 , further comprising: forming an etch stop layer at the fifth depth by performing ion implantation through the first surface of the first substrate, after forming the shallow trench isolation and before forming the at least one transistor.

5. The method of claim 1 , wherein thinning the first substrate from the second surface of the first substrate comprises grinding the second surface to a sixth depth, performing a wet etching on the grounded surface to a second depth, the second depth being a distance from the second surface to the first surface of the first substrate after the wet etching, the second depth being greater than the first depth.

6. The method of claim 2 , wherein the second depth is substantially same as the third depth.

7. The method of claim 2 , wherein the second depth is substantially same as the fourth depth.

8. The method of claim 2 , wherein the second depth is substantially same as the fifth depth.

9. The method of claim 1 , wherein thinning the first substrate comprises:

performing backside grinding on the second surface of the first substrate; and

performing first wet etching on the second surface of the first substrate to a second depth.

10. The method of claim 9 , further comprising, after performing the first wet etching, performing chemical mechanical polishing on the second surface of the first substrate, stopping at the pad layer of the shallow trench isolation.

11. The method of claim 1 , wherein the transistor includes a source, a drain, and a gate, and wherein the source and the drain are disposed below the first surface of the first substrate, and the gate is disposed above the first surface of the first substrate.

12. The method of claim 1 , wherein the first substrate comprises a bulk silicon substrate.

13. The method of claim 10 , further comprising, after performing the first wet etching and before performing the chemical mechanical polishing, performing low-temperature annealing of the first substrate including the carrier substrate.

14. The method of claim 1 , wherein the shallow trench isolation further comprises a main structure layer surrounded by the pad layer.

15. The method of claim 14 , wherein the pad layer comprises silicon oxide and the main structure layer comprises silicon nitride.