Method of manufacturing thin-film transistor
View Patent ↗According to one embodiment, a method of manufacturing a thin-film transistor includes forming a semiconductor layer on a gate electrode with an insulating layer 12 being interposed, forming interconnect formation layers on the semiconductor layer, forming a plurality of interconnects and electrodes by patterning the interconnect formation layers through etching, patterning the semiconductor layer in an island shape through etching after forming the electrodes, exposing a channel region of the semiconductor layer by etching a part of the electrodes on the semiconductor layer, and forming a protective layer so as to overlap the interconnects, the electrodes and the semiconductor layer having the island shape.
1. A method of manufacturing a thin-film transistor, the method comprising:
forming a semiconductor layer above a gate electrode with an insulating layer being interposed;
forming an interconnect formation layer on the semiconductor layer;
forming a first resist on the interconnect formation layer and forming a plurality of interconnects and a part of each of electrodes by patterning the interconnect formation layer through etching in a state that the first resist covers the interconnect formation layer;
patterning the semiconductor layer in an island shape through etching after forming the electrodes;
removing the first resist after patterning the semiconductor layer;
forming a second resist on the interconnects, a part of the sidewall of the electrodes, and the insulating layer, and exposing a channel region of the semiconductor layer by etching a part of the electrodes on the semiconductor layer in a state that the second resist covers the interconnects, a part of the sidewall of the electrodes, and the insulating layer;
removing the second resist after exposing the channel region of the semiconductor layer; and
forming a protective layer so as to overlap the interconnects, the electrodes and the semiconductor layer having the island shape.
2. The method of claim 1 , wherein
the interconnect formation layer is formed by stacking a plurality of metal layers.
3. The method of claim 2 , wherein
the semiconductor layer is formed of an oxide containing at least one of indium (In), gallium (Ga) and zinc (Zn).
4. The method of claim 3 , wherein
a sidewall of the interconnects and a sidewall of the electrodes are formed so as to have a taper angle of 45 to 75°.