Automatic delay-line calibration using a replica array
View Patent ↗A computer memory system, delay calibration circuit, and method of operating a delay calibration circuit are provided. The disclosed method includes providing a delay-line ring oscillator on silicon of a chip, providing at least one counter on the silicon of the chip, and measuring a chip-specific delay for performing an operation with the chip by synchronizing the at least one counter and operation of the delay-line ring oscillator with a timing trigger.
1. A computer memory system, comprising:
a memory array comprising a plurality of memory cells; and
a delay calibration circuit comprising a delay-line that is used to measure a chip-specific delay between when a bitline is discharged by a bitcell and when a sense amplifier is used to detect a memory value from the memory array, wherein the delay calibration circuit triggers the delay-line to begin measuring the chip-specific delay in response to a timing trigger, wherein the delay calibration circuit further comprises a first counter, a second counter, and a clock signal, wherein the first counter is connected to the delay-line, wherein the second counter is connected to the clock signal, and wherein the timing trigger corresponds to a time where the clock signal is started and the first and second counters both begin counting at substantially the same time.
2. The computer memory system of claim 1 , wherein both the first counter and second counter continue counting until the clock signal reaches a predetermined value at which time the first counter is stopped and a final value of the first counter provides an indication of the chip-specific delay with respect to the clock signal.
3. The computer memory system of claim 1 , wherein the delay-line comprises a delay-line ring oscillator.
4. The computer memory system of claim 1 , wherein the delay calibration circuit measures a delay associated with a read operation and/or a write operation in which a chip is used to read data from and/or write data to the memory array.
5. The computer memory system of claim 1 , wherein the memory array is provided on a chip.
6. The computer memory system of claim 1 , wherein the plurality of memory cells comprise a plurality of different types of memory cells.
7. The computer memory system of claim 1 , wherein the delay calibration circuit and the memory array are provided on a common piece of silicon.
8. The computer memory system of claim 1 , wherein the chip-specific delay is stored to a lookup table.
9. A delay calibration circuit, comprising:
a delay-line that is used to measure a chip-specific delay between when a bitline is discharged by a bitcell and when a sense amplifier is used to detect a memory value from a memory array, wherein the delay-line is triggered to begin measuring the chip-specific delay in response to a timing trigger;
a first counter connected to the delay-line;
a second counter; and
a clock signal, wherein the second counter is connected to the clock signal, and wherein the timing trigger corresponds to a time where the clock signal is started and the first and second counters both begin counting at substantially the same time.
10. The delay calibration circuit of claim 9 , wherein both the first counter and second counter continue counting until the clock signal reaches a predetermined value at which time the first counter is stopped and a final value of the first counter provides an indication of the chip-specific delay with respect to the clock signal.
11. The delay calibration circuit of claim 9 , wherein the delay-line comprises a delay-line ring oscillator.
12. The delay calibration circuit of claim 9 , wherein a delay associated with a read operation and/or a write operation is measured in which a chip is used to read data from and/or write data to a memory array.
13. The delay calibration circuit of claim 12 , wherein the memory array is provided on a chip.
14. The delay calibration circuit of claim 13 , wherein the memory array includes a plurality of memory cells of different types.
15. The delay calibration circuit of claim 9 , wherein the chip-specific delay is stored to a lookup table.
16. A system, comprising:
a memory array; and
a delay calibration circuit, comprising:
a delay-line that is used to measure a chip-specific delay between when a bitline is discharged by a bitcell and when a sense amplifier is used to detect a memory value from the memory array, wherein the delay-line is triggered to begin measuring the chip-specific delay in response to a timing trigger;
a first counter connected to the delay-line;
a second counter; and
a clock signal, wherein the second counter is connected to the clock signal, and wherein the timing trigger corresponds to a time where the clock signal is started and the first and second counters both begin counting at substantially the same time.
17. The system of claim 16 , wherein both the first counter and second counter continue counting until the clock signal reaches a predetermined value at which time the first counter is stopped and a final value of the first counter provides an indication of the chip-specific delay with respect to the clock signal.
18. The system of claim 16 , wherein the delay-line comprises a delay-line ring oscillator.
19. The system of claim 16 , wherein a delay associated with a read operation and/or a write operation is measured in which a chip is used to read data from and/or write data to a memory array.
20. The system of claim 16 , wherein the chip-specific delay is stored to a lookup table.